Junghyun Ham

Broadband Doherty Power Amplifier Based on Asymmetric Load Matching Networks

This brief presents asymmetric load matching networks for broadband Doherty power amplifiers (DPAs). The output combiner consists of two λ/4 impedance transformers with optimized characteristic impedance values in order to provide a load modulation at a high output power level; the bandwidth limitation for efficiency at the back-off power level can be then mitigated. For a proper load modulation with the proposed output combiner, asymmetric load matching networks between the carrier and peaking amplifiers are proposed. The input and output matching networks were designed using balanced open stubs, which are more insensitive to frequency than unbalanced open stubs. For the load matching networks, two-section matching networks were adopted. The designed and implemented broadband DPA showed a fractional bandwidth of 23.5% (from 750 to 950 MHz). It also showed measured efficiency values of higher than 55.4% at the peak power level and 51.5% at the 6-dB back-off power level, respectively. For the operational frequency range, a peak output power value of higher than 48 dBm and a gain of 14-15.8 dB were achieved.

Adaptive TX Leakage Canceler for the UHF RFID Reader Front End Using a Direct Leaky Coupling Method

This paper presents a new adaptive leakage canceler based on a direct leaky coupling method for an RF front-end circuit of an ultrahigh-frequency radio-frequency identication (UHF RFID) reader. For better receiver sensitivity, the leakage signal from a transmitter (TX) to a receiver (RX) should be suppressed. Compared with conventional methods, the proposed TX leakage canceler has a much simpler circuit configuration due to the direct leaky coupling circuit (LCC) and the phase shifter on the RX path. The LCC includes a variable resistor, a variable capacitor, and an inductor, which allow us to control the magnitude and the phase of the coupled TX signal. The phase shifter that is located on the RX path even before the low-noise amplifier controls the phase of the TX leakage signal. For the worldwide RFID bands that spans from 840 to 960 MHz, the canceler must be adaptively controlled by using a microcontroller and control circuits. For the experimental verification, an RF front-end circuit with the proposed adaptive TX leakage canceler was designed and implemented for the UHF RFID reader. The implemented RF front-end block occupies only 54 ×54 mm2, except for the control block. From 840 to 960 MHz, the adaptively controlled RF front-end circuit exhibited significant cancelation characteristics for the TX-RX leakage signals. This results in more than twice longer reading distances for the commercial RFID tags compared with the cases without the adaptive canceler.

A CMOS Envelope Tracking Power Amplifier for LTE Mobile Applications

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

High-Efficiency Power Amplifier Using an Active Second-Harmonic Injection Technique Under Optimized Third-Harmonic Termination

This brief presents an active second-harmonic injection technique to improve the efficiency and bandwidth for high-efficiency power amplifiers (PAs). An optimum third-harmonic termination condition was examined for higher efficiency after the second-harmonic injection using a multiharmonic load-pull simulation. It was determined that the optimum third-harmonic termination is the same as that of the inverse class-F PA. Based on this result, a high-efficiency PA with an optimized third-harmonic termination for the second-harmonic injection was designed for a center frequency of 1 GHz as a main amplifier. The overall system requires an auxiliary second-harmonic amplifier and a diplexer between the main and auxiliary PAs. The PA with an optimized third-harmonic termination for the second-harmonic injection was implemented using a 10-W GaN high-electron-mobility transistor for both the main and auxiliary power stages. Compared with the PA without second-harmonic injection, the bandwidth with a power-added efficiency of more than 80% is extended from 60 (960-1020 MHz) to 180 MHz (880-1060 MHz) after the second-harmonic injection.

400 W broadband power amplifier using transmission-line transformers with 1:8 impedance transformation ratio

Abstract This paper presents a broadband high-power amplifier using transmission-line transformers with a high impedance transformation ratio. Two series-connected transformers with 1:8 and 1:1 impedance transformation ratios are used at the load network of a single-balanced high-power amplifier to match the low load impedance in broadband. The same transformer configuration is also used at the input network. A negative feedback is applied to improve the gain flatness and to increase the stability over the broadband. In order to validate the proposed circuit structure, a broadband high-power amplifier is designed and implemented to achieve an output power of more than 400 W in the frequency band of 30 to 500 MHz. The implemented power amplifier exhibits a flat gain response within 1.80 dB at an average of 19.1 dB and high power-added efficiencies of 28.0 to 56.9 at an output power of 400 W over the entire frequency band.

CMOS Power Amplifier Integrated Circuit With Dual-Mode Supply Modulator for Mobile Terminals

A CMOS power amplifier integrated circuit with an optimized dual-mode supply modulator is presented. The dual-mode supply modulator, based on a hybrid buck converter consisting of a wideband linear amplifier and a highly efficient switching amplifier, provides two operation modes: envelope tracking (ET) for high average output power and average power tracking (APT) for low output power. For the APT mode, the linear amplifier is switched off and the switching amplifier operates as a normal buck converter to supply DC voltage to the power amplifier according to the average output power. The optimum switch sizes of the switching amplifier were analyzed and applied for each operation mode for higher efficiency. An integrated circuit with a power amplifier and the dual-mode supply modulator was designed and fabricated using a 0.18-μm CMOS process for LTE applications at a frequency of 0.78 GHz. For the 16-QAM uplink LTE signal, the measured efficiency with an ET mode is as high as 45.4%, which is 7.0% higher than that from the stand-alone power amplifier at an average output power of 24 dBm. An efficiency of 14.1% was achieved with an APT mode at an average output power of 9 dBm. This is 3.2% higher than that with the ET mode.

Dual Bias Modulator for Envelope Tracking and Average Power Tracking Modes for CMOS Power Amplifier

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a 0.18-㎜ CMOS process for the 1.75 ㎓ band. For the 16-QAM LTE signal with a peakto-average power ratio of 7.3 ㏈ and a bandwidth of 5 ㎒, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 ㏈, and an adjacent channel leakage power ratio of -30 ㏈c at an average output power of 22 ㏈m, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 ㏈m.

A CMOS envelope tracking power amplifier for 4G LTE mobile terminal applications

An envelope tracking power amplifier (ET PA) using a standard CMOS process for the 3GPP long-term evolution mobile terminals is presented. An efficiency of the CMOS power amplifier for the modulated signals can be improved combining with a highly efficient and wideband CMOS bias modulator. The CMOS PA has a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator has a hybrid structure which consists of a linear stage and a switching stage. The variable load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, the ET PA delivers a PAE of 41.7 % at an average output power of 24 dBm, which is 5.3 % points higher than that of the power amplifier alone at the same average output power and linearity.

Low-Power and High-Efficiency Class-D Audio Amplifier Using Composite Interpolation Filter for Digital Modulators

This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital deltasigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of 16 6 and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.