Junji Nakagoshi

Deadlock-free fault-tolerant routing in the multi-dimensional crossbar network and its implementation for the Hitachi SR2201

We have developed a hardware detour path selection facility for the Hitachi SR2201 parallel computer, which uses a multi-dimensional crossbar as an inter-processor network to ensure operating efficiency and high reliability when a part of the network is faulty. When this hardware facility is used, packets are transmitted to their destination along alternative paths to avoid the fault. However, changing the routing may cause deadlock. This paper describes a deadlock-free fault-tolerant routing scheme that can be used by the detour path selection facility to avoid deadlock, and its implementation for the SR2201.

Reducing Network Hardware Quantity by Employing Multi-Processor Cluster Structure in Distributed Memory Parallel Processors

This paper describes a cluster structure to reduce the amount of network hardware in distributed memory parallel processors. The expected reduction in the data transfer rate as the number of nodes is reduced is avoided by raising the transfer rate of each path. Calculations for typical application programs show that clustering can reduce the hardware quantity by 40% provided that inner-cluster parallel processing efficiency is sufficiently high.

Effective simulation for the giga-scale massively parallel supercomputer SR2201

A high performance parallel network simulation environment was developed in the SR2201 project, The SR2201 is one of the highest performance massively parallel supercomputers in the world. The enhanced simulation algorithm achieved a 2.4 times increase in simulation speed compared with conventional simulation methodology. A 98% detection rate for all design errors before physical design contributed to the shortening of development time.