Junmin Jiang

20.5 A 2-/3-phase fully integrated switched-capacitor DC-DC converter in bulk CMOS for energy-efficient digital circuits with 14% efficiency improvement

Reducing the supply voltage of digital circuits to the sub- or near-threshold regions minimizes dynamic power consumption and achieves better efficiency [1]. This technique is widely used in energy-efficient applications, and is especially beneficial for wirelessly powered devices such as wearable electronics, biomedicai implants and smart sensor networks. Such devices have long standby times and battery-less operation is highly desirable. As shown in Fig. 20.5.1, for a typical wireless power transmission system, there is a gap between the rectified VIN (>2V) and the low supply voltage VOUT (<;700mV) for powering up energy-efficient digital circuits. To bridge this voltage gap without sacrificing compact size, fully integrated power converters with a low voltage conversion ratio (M=Vout/VIN) and high efficiency are needed. However, a low M results in low efficiency for linear regulators and fully integrated buck converters. On the other hand, fully integrated switched-capacitor power converters (SCPCs) are good alternatives that can achieve high efficiency at low M in low power applications [2-5].

20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors

Inspired by The Square of Vatican City, a fully integrated step-down switched-capacitor DC-DC converter ring with 100+ phases is designed with a fast dynamic voltage scaling (DVS) feature for the microprocessor in portable or wearable devices. As shown in Fig. 20.4.1, this symmetrical ring-shaped converter surrounds its load in the square and supplies the on-chip power grid, such that a good quality power supply can be easily accessed at any point of the chip edges. There are 30 phases on the top edge and 31 phases on each of the other 3 edges, making 123 phases in total. The phase number and unit cell dimensions of this architecture can easily be adjusted to fit the floor plan of the load. The pads of the converter-ring are placed at the corners, and will not affect the pads of the load. Moreover, by using the proposed VDD-controlled oscillator (VDDCO), the frequency of which is controlled by varying its supply voltage, a hitherto unexplored feature of the multiphase DC-DC architecture is exposed: the control-loop unity gain frequency (UGF) could be designed to be higher than the switching frequency.

Analysis and Design Considerations of Integrated 3-Level Buck Converters

This paper presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters. Under ideal conditions, the voltage conversion ratio, the output voltage ripple and, in particular, the systems loop-gain function are derived. Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under these conditions, the voltage conversion ratio, the voltage across the flying capacitor and the power efficiency are analyzed and verified with Cadence simulation results. The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method. The derived loop-gain functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results.

A digitally-controlled 2-/3-phase 6-ratio switched- capacitor DC-DC converter with adaptive ripple reduction and efficiency improvements

A digitally controlled 2-/3-phase 6-ratio switched-capacitor (SC) DC-DC converter with low output voltage ripple and high efficiency is presented. Operating with a wide input voltage range of 1.6V to 3.3V, this SC converter can deliver a maximum power of 250mW to an output of 0.5V to 3V. Six voltage conversion ratios (VCRs) can be generated with only 2 flying capacitors by using 2- or 3-phase operation. Compared with a 2-phase SC converter, the maximum efficiency improvement is 20%. An adaptive ripple reduction scheme is proposed to achieve 4 times reduction in the output voltage ripple. Complexity of controller design is reduced by using digital synthesis and the technique is scalable. Fast loop response is achieved by synchronized hysteretic control. The converter achieves a peak efficiency of 91%.

Digital 2-/3-Phase Switched-Capacitor Converter With Ripple Reduction and Efficiency Improvement

This paper presents a digitally controlled 2-/3-phase 6-ratio switched-capacitor (SC) dc-dc converter with low output voltage ripple and high efficiency. To achieve wide input and output voltage ranges, six voltage conversion ratios are generated with only two discrete flying capacitors by using both 2- and 3-phase operations. An adaptive ripple reduction scheme is proposed to achieve up to four times reduction in the output voltage ripple. The complexity of controller design is reduced by using digital synthesis, and the technique is scalable with process. Fast loop response is achieved by using synchronized hysteretic control. The SC converter was fabricated in a 0.13-

A self-powered zero-quiescent-current active rectifier for piezoelectric energy harvesting

\mu \text{m}

Methods for measuring loop-gain function of high-frequency DC-DC converters

CMOS process. It can deliver a maximum power of 250 mW to an output of 0.5–3 V with a wide input voltage range of 1.6–3.3 V. Compared to an SC converter with only 2-phase operation, the maximum efficiency improvement is 20%. The converter achieves a peak efficiency of 91%.

A low-dropout regulator with power supply rejection improvement by bandwidth-zero tracking

A self-powered zero-quiescent-current active rectifier for piezoelectric energy harvesting is proposed. It consists of two cross-biased PMOS transistors and two active diodes. To achieve zero quiescent-current, a biasfree clamping circuit is designed to clamp the drain-source voltage of the NMOS transistor of the active diode. Post-simulation and measurement results show that the proposed active rectifier achieves an efficiency improvement of more than 40% vs. the ordinary full-bridge rectifier; the power transferred by the rectifier from the piezoelectric energy harvester (PEH) to the storage capacitor is increased significantly, especially even when the output power of PEH is low.

Analysis of two-phase on-chip step-down switched capacitor power converters

This paper analyzes and compares two methods to measure the loop-gain function of high-frequency DC-DC converters. A guideline is given on the measurement setups, component selection and situations that should be avoided. The correctness of the presented methods is verified by measuring the gain and phase transfer function of a 50-MHz 3-level buck converter. The measurement results fit well with the simulation results under a maximum measuring frequency of 20 MHz.

A Multiphase Switched-Capacitor DC–DC Converter Ring With Fast Transient Response and Small Ripple

This paper presents a low-dropout regulator (LDO) with low quiescent current, small area, and power supply rejection (PSR) improvement, implemented in 0.35μm CMOS process. A zero that tracks the unity gain frequency is employed in the feedback loop using a 1pF compensation capacitor. An improved intermediate stage is designed to split the low frequency pole and drive the power MOSFET. With no equivalent series resistor (ESR) zero requirement, the minimum DC gain and phase margin are 76dB and 70°, respectively. The proposed LDO dissipates 20μA at no-load condition and 385μA at full-load condition. The effective die area is 180×75μm2 that is comparable to the size of a standard I/O. Thus, integrating the proposed LDO in system is flexible.