Junyan Tan

Generation of emulation platforms for NoC exploration on FPGA

NoC (Network on Chip) architecture exploration is an up to date problem with todays multimedia applications and platforms. The presented methodology gives a solution to easily evaluate timing and resource performances tuning several architectural parameters, in order to find the appropriate NoC architecture with a unique emulation platform. In this paper, a design flow that generates NoC-based emulation platforms on FPGA is presented. From specified traffic scenarios, our tool automatically inserts appropriate IP blocks (emulation blocks and routing algorithm) and generates an RTL NoC model with specific and tunable components that is synthesized on FPGA.

Exploration of an adaptive NoC architecture on FPGA dedicated to multi and hysperspectral algorithm for art authentication

This paper presents an adaptive communication architecture dedicated to multispectral and hyperspectral imaging algorithms for art authentication for embedded and portable systems. The communication architecture is a Network on Chip (NoC) architecture implemented on a FPGA (Field Programmable Gate Array). From several parameters extracted from the algorithm, an emulation platform is designed to explore performances of the communication architecture. This emulation architecture contains the NoC architecture associated to generator and receptor traffic blocks to simulate data transfers inside the NoC. Several traffic scenarios extracted from the algorithm are explored. Timing and resource performances are analyzed for several parameterizations of the architecture to identify the adapted architecture and their limitations.

A predictive and parametrized architecture for image analysis algorithm implementations on FPGA adapted to multispectral imaging

The presented parameterised and predictive architecture is dedicated for image analysis algorithms implementations on FPGAs. Image analysis algorithms have shared characteristics. These characteristics serve as a basis for the presented parameterised architecture. The architecture design is based on the linear effort property and reusable IP. For a new algorithm implementation, adaptations only concern a small part of the entire architecture. New IPs are developed in handel-C using the DK design suite tool provided by Celoxica. The design space exploration (DSE) is made off-line with the use of prediction models which results in a shorter design time and the generated architecture will satisfy the given constraints. An example of the design process is presented with the multispectral imaging implementation instead of the particle image velocimetry (PIV) algorithm.

Case study: Deployment of the 2D NoC on 3D for the generation of large emulation platforms

The evaluation of Network-On-Chip (NoC) architectures is an up to date problem in the design of System-on-Chip. Emulation on FPGA (Field Programmable Gate Array) is used to cover all possible NoC solutions in a reduced exploration time. Emulation requires multi-FPGA platform as the resources for large NoC is important and cannot be handling by one FPGA. In the same time, SoC community is exploring 3D technology for the next generation of large SoC with 3D NoC, making emulation more complex. This paper presents a case study of the deployment of the 2D NoC structure to 3D. A design flow is proposed for the automatic generation of a NoC targeting 3D on multi-FPGAs. The flow integrates emulation blocks used for the validation and exploration on the NoC. With this automatic aided tool, the designer can evaluate and explore the NoC architecture and extract performances of the NoC regardless of the multi-component platform. One may expect a communication performance improvement using an adapted partitioning of the NoC, as highlighted by the results given in this paper.