Young-Sun Min

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers

Todays explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability, and cost competitiveness. V-NAND has also eliminated the cell-to-cell interference problem by forming an atomic layer for charge trapping [2], which enables further technology scaling. However, the etching technology required for creating a channel hole cannot keep up with the market-driven WL stack requirement. Therefore, total mold height reduction is unavoidable and this creates several problems. 1) reduced mold height increases resistance and capacitance for WLs due to the thinner layers being used. 2) channel hole critical dimension (CD) variation becomes problematic because the additional mold stack height aggravates uniformity, thereby producing WL resistance variation. Consequently, read and program performance degradation is inevitable, furthermore their optimization becomes more challenging.

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated WL loading and variations are discussed. To enhance performance, reverse read scheme and variable-pulse scheme are presented to cope with nonuniform WL characteristics. For improved performance, dual state machine architecture is proposed to achieve optimal timing for BL and WL, respectively. Also, to maintain robust IO driver strength against PVT variations, an embedded ZQ calibration technique with temperature compensation is introduced. The chip, fabricated in a third generation of V-NAND technology, achieved a density of 2.6 Gb/mm2 with 53.2 MB/s of program throughput.

Comparative study of WL driving method for high-capacity NAND flash memory

In this work, we demonstrated comparative study of the WL driving method in 256-Gb VNAND with 16KB page size. The fixed pulse width (FPW) which uses the fixed WL pulse width with incremental voltage has a large tPROG due to the decreased Vth shift in the later ISPP loop. The incremental pulse width (IPW) which incrementally increases the programming voltage and pulse width overcomes the small Vth shift problem in the later loop. In addition, the optimization methods for FPW and IPW are presented to obtain a small tPROG considering the narrow Vth distribution of NAND cell after programming operation. The comparison of the WL driving methods is performed by HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 16KB page size.

WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory

In this work, we compared the WL driving schemes in 512 Gb planar NAND with 32 KB page size. In the conventional WL driving scheme, the rising time of the selected WL voltage is very large because of the large coupling capacitance between the selected and unselected WLs. The WL under-driving scheme (WLUDS) reduces the effect of coupling capacitance by using the 2-phase control of unselected WL voltage. However, when WLUDS is used, the relationship between the rising time and overshoot of the selected WL voltage should be considered in order to achieve the small rising time Therefore, we proposes a novel implementation method for WLUDS that controls the under-driving voltage and under-driving timing by using the decremental step voltage and incremental step time (DSVIST) to enhance the rising time considering the overshoot constraint. The HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 32 KB page size shows that the rising time in the proposed WLUDS with DSVIST is improved to 988 μs compared to 1206 μs in the conventional WL driving scheme.