Jury Sandrini

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

This work presents the co-integration of resistive random access memory crossbars within a 180 nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of-the-Line. Two different strategies, consisting in insertion of an Al2O3 tunnel barrier layer and the design of a dedicated CMOS read circuit, have been developed in order to increase the cell high-to-low resistance ratio of a factor of 1000 and to reduce the sneak-path current effects by one order of magnitude. The ReRAM cells have been integrated directly on a standard CMOS foundry chip, enabling low cost ReRAM-CMOS integration. The integrated memories show a set and reset voltages of -1 and 1.3 V, respectively. The measured operating voltages are compatible for low-voltage applications.

Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology

This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operation, and a WRITE protocol to minimize the current at each row and column lines. The presented circuit has been designed in 180nm standard CMOS technology based on the electrical characteristics of fabricated ReRAM devices.

A ultra-low-power FPGA based on monolithically integrated RRAMs

Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay and power consumption numbers. With the ability of being monolithically integrated with CMOS chips, Resistive Random Access Memories (RRAMs) enable high-performance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs as well as the improved tolerance to power supply reduction, RRAM-based routing multiplexers can be used to significantly reduce the power consumption of FPGA systems with no performance compromises. By evaluating the opportunities of ultra-low-power RRAM-based FPGAs at the system level, we see an improvement of 12%, 26% and 81% in area, delay and power consumption at a mature technology node.

Chip-level CMOS co-integration of ReRAM-based non-volatile memories

This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180nm CMOS technology chips. The proposed integration method enables low-cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory systems. We propose to use W plugs, already present as vias in CMOS technology, as the ReRAM bottom electrodes. The resistance switching layer, WOx, is obtained by the mask-free rapid thermal oxidation of the W plug surface. With this method, we are able to fabricate 280nm non-volatile memory devices without any additional high-resolution lithography. The integrated memory devices operate at 300 μA, with a high resistance state of 0.6MΩ and low resistance state of 4 kΩ. The electrical characteristics confirm the possibility to integrated non-volatile memories on the back-end-of-the-line of standard CMOS chips, enabling low-cost integration of the memory components with the CMOS driving circuitry.

Effect of Hf metal layer on the switching characteristic of HfOX-based Resistive Random Access Memory

In this study, we propose the insertion of an ultrathin Hf layer at the interface between TiN (top electrode) and HfOx (electrolyte), and then studied its effect on the device electrical properties. In order to obtain the desired switching characteristics, the Hf layer thickness must be precisely engineered. The device with optimized Hf layer thickness exhibits better uniformity and lower forming voltage. This could be explained by the role of Hf layer in the creation of permanent oxygen vacancies in the oxide layer, which facilitates the switching phenomena.

Evolution of oxygen vacancies under electrical characterization for HfO x -based ReRAMs

Recently, studies on ReRAMs and their reliability have received increased attention. The reliability issue is due to the nature of oxygen vacancies behaviour under biasing conditions which necessitate further studies to achieve an in-depth understanding. In this work, we fabricated several HfOx ReRAM devices with different structure, material, and thickness, followed by a study of their electrical characteristics under DC biasing. We show an improvement in the switching parameters through engineering of the device structure. Moreover, we demonstrate a certain required thickness for the oxide layer for the ease of oxygen vacancies relocations, thinner oxide layer led to the common ReRAMs performance failure in the low resistance state.

Effect of metal buffer layer and thermal annealing on HfO x -based ReRAMs

In this paper, we investigate different methods and approaches in order to improve the electrical characteristics of Pt/HfOx/TiN ReRAM devices. We discuss the improvement of the ReRAM electrical characteristics after the insertion of a Hf and Ti buffer layer. As a result, the resistance window increases more that 10 times, and the set and reset voltages decrease both in absolute value and variability. Furthermore, we show the influence of an annealing step at different temperatures on the Pt/HfOx/Hf/TiN memory devices on forming voltage and HRS. Considering the importance of achieving high density memory, we demonstrated the possibility of multi-level resistance state in the fabricated devices bu controlling the enforced compliance current. In addition, we show the endurance characteristic of the fabricated memories and their error rate. Finally, we report the transient behavior of the memory devices, investigating the device speed and switching mechanism.