Tugba Demirci

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

This work presents the co-integration of resistive random access memory crossbars within a 180 nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of-the-Line. Two different strategies, consisting in insertion of an Al2O3 tunnel barrier layer and the design of a dedicated CMOS read circuit, have been developed in order to increase the cell high-to-low resistance ratio of a factor of 1000 and to reduce the sneak-path current effects by one order of magnitude. The ReRAM cells have been integrated directly on a standard CMOS foundry chip, enabling low cost ReRAM-CMOS integration. The integrated memories show a set and reset voltages of -1 and 1.3 V, respectively. The measured operating voltages are compatible for low-voltage applications.

Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology

This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operation, and a WRITE protocol to minimize the current at each row and column lines. The presented circuit has been designed in 180nm standard CMOS technology based on the electrical characteristics of fabricated ReRAM devices.

Chip-level CMOS co-integration of ReRAM-based non-volatile memories

This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180nm CMOS technology chips. The proposed integration method enables low-cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory systems. We propose to use W plugs, already present as vias in CMOS technology, as the ReRAM bottom electrodes. The resistance switching layer, WOx, is obtained by the mask-free rapid thermal oxidation of the W plug surface. With this method, we are able to fabricate 280nm non-volatile memory devices without any additional high-resolution lithography. The integrated memory devices operate at 300 μA, with a high resistance state of 0.6MΩ and low resistance state of 4 kΩ. The electrical characteristics confirm the possibility to integrated non-volatile memories on the back-end-of-the-line of standard CMOS chips, enabling low-cost integration of the memory components with the CMOS driving circuitry.

A single-chip 2048×1080 resolution 32fps 380mW trinocular disparity estimation processor in 28nm CMOS technology

This paper presents a single-chip trinocular disparity estimation processor, capable of computing in real-time up to 2048×1080 resolution depth maps at 32fps with up to 256-pixel disparity range using two/three CMOS camera sensors. The most important feature of the presented design is that the chip is based on a trinocular adaptive window matching process that requires very limited on-chip memory, and completely avoids the usage of any external memory. Moreover, it provides the highest reported disparity range capability at the lowest power consumption and highest frame rate, while computing high-quality disparity results. It features a stream-in/out interface to be easily integrated in existing vision systems, without additional overhead, and offers a dynamically scalable tradeoff between throughput, resolution and disparity range. The single-chip is fabricated in 28nm CMOS technology, has a die area of 5.96mm2 and a power consumption of 380mW at 300MHz clock frequency.

3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation

In this paper we present the design of a temperature compensated low-tune-voltage-sensitive CMOS ring oscillator in 40nm standard CMOS technology. The oscillator has an overall frequency range from 3.1 GHz to 3.6 GHz. The effect of temperature variations on the frequency span has been tuned out by an IPTAT (inversely proportional to absolute temperature) current reference. In this work, using a coarse-fine tuning mechanism lowers the tune range sensitivity of the oscillator, which is usually represented as KVCO. The achieved KVCO is around 490 MHz/V with 400 mV tune voltage sweep. The area and the power consumption of the ring oscillator are 0.0056 mm2 and 0.9 mW.

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

In this paper we present the design of a programmable frequency divider in 28 nm FD-SOI CMOS technology. It consists of the cascade of a divide-by-2 cell and divide-by-2/3 blocks. The final circuit is capable of dividing by even numbers between 128 and 254. The forward-body-bias property of the process and the differential-cascode voltage-switch-logic (DCVSL) family are used to achieve high operation speed. The proposed circuit achieves a maximum operating frequency of 20 GHz at 1 V supply voltage. And the area and the power consumption of the programmable divider are 1815 μm2 and 4.35 mW, respectively.