Younghwan Bae

Automatic interface synthesis based on the classification of interface protocols of IPs

In a system on a chip (SoC) design, we use an IP-based design methodology to reduce design time. An interface circuit design is one of the most essential factors in IP-based design. However, it is not easy to generate interface circuits because IPs have various characteristics. For example, one IP may send only one outstanding address in a burst but another IP may need one address for each transfer in a burst. IPs also use different clock frequencies or different data widths. It is necessary to analyze the interface protocols of each IP to consider and resolve these differences during synthesis. In this paper, we categorize the various interface protocols and use the synthesis algorithm to select the appropriate structure based on the categorizations, clock frequencies, and data width differences of the IPs. Through the experiments, we show that we could automatically generate interface circuits for IPs with different clocks, different data widths, and no address concepts. Experiments also show the pros and cons of two structures based on the comparisons of the synthesis results of several IP pairs which could be employed between two alternative structures, namely, product FSM-based structure and FSMD-like structure.

Performance analysis of NoC structure based on Star-Mesh Topology

The fabrication technology development of the semiconductor leads the evolutional design methodology to reconsider the efficiency, such as reusability and scalability. NoC (Network On Chip) is the remarkable alternative to support this trend that provides the interface between IPs. In this paper, the general performance analysis through considering the characteristic of the NoC was done with the proposed NoC topology. Besides, the performance at the topology which is the specification application, 4-channel H.264 decoder, was predicted in advance. We could build the environment facilitating the adjustment of the buffer size and mapping of IP with this scheme.

Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols and Matching Information

Automatic interface synthesis generates product FSM from interface FSMs of IP. But complicated interface FSM may lead to a very large product FSM which results in large interface circuits. So we propose a simplified interface FSM description scheme where transactions are represented based on transfers and several parameters. In addition, the interface circuit is generated by considering only those transactions which are involved in matching information. By virtue of matching information we could generate the interface circuits which may not be easy to generate with previous methods due to inability to consider the differences in characteristics of interface protocols of IP. Through experiments we observed that our description scheme helps reduce the size of interface circuits and our synthesis method correctly generates the interface circuits between IPs with different characteristics.

Automatic synthesis of interface circuits from simplified IP interface protocols

Most approaches to interface synthesis take two interface FSMs including transactions or burst, derive a product FSM and generate an interface circuit from the product FSM. With these methods, it could be difficult and complicated to describe interface FSM of IP especially when IP has many transactions. Additionally, such descriptions may lead to a very large product FSM which results in large interface circuits. We propose a simplified interface FSM description scheme where transactions are represented based on transfers and several parameters. Since all transactions supported by IP may not be used in the system, the synthesis algorithm is designed to consider only those transactions which are involved in parameter matching. Through experiments we observed that our description scheme helps reduce the size of interface circuits and our synthesis method correctly generates the interface circuits.

Star-Mesh NoC based multi-channel H.264 decoder design

In this paper we described the architectural exploration of Star-Mesh NoC based multi-channel H.264 decoder. The Star-Mesh NoC is comprised of local star switch and global mesh switch. By analyzing data transfers among the processors, IPs, and memories, we partitioned IPs into clusters to map then to Star-Mesh NoC architecture. In order to enhance data parallelism and NoC utilization, H.264 decoder IPs with much data traffic are mapped to star switch and shared memory is connected to mesh switch where star switch connected to mesh switch with 1-hop. We explored several mapping architecture to achieve improvement of the system throughput.

Latency optimization for NoC design of H.264 decoder based on self-similar traffic modeling

In this article, we present analytical method to evaluate the NoC design of H.264 decoders latency based on the self-similar traffic models of all 12 IPs. The traffic models are generated by using the superposition of four 2-state Modulated Markov Poisson Process (MMPP) and the real traced data transaction between IPs. The optimization engine is utilized to automatically allocate IPs on the desired routers to achieve the minimal latency.

The Optimized Tree-based Network on Chip Topologies for H.264 Decoder Design

A new chip design paradigm, so called network on chip, has been introduced based on the demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks. In this paper, the H.264 decoder designed with three differently heterogenous tree-based network topologies are proposed. The topologies are designed so as to maximize the network throughput in accordance with the required transaction data between the functional modules of the H.264 decoder. This paper also evaluates these three topologies by comparing them to other regular topologies such as 2-D mesh and fat-tree with respects to throughput, power consumption and size. The simulated throughputs and various switch configurations are used as the inputs of the power modelling tool, known as Orion model. Hence, the static powers, areas, and dynamic energies of three topologies are calculated. The experiment results show that our tree-based topologies offer similar throughputs as fat-tree does and much higher throughputs compared to 2-D mesh while us less chip areas and power consumptions

Throughput aware mapping for network on chip design of h.264 decoder

Network-on-Chip (NoC) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, we present the queuing theory based model for router to evaluate the performance of NoC in terms of drop probability, throughput and energy consumption. Then we apply the linear programming to optimize the allocation of the heterogeneously functional blocks (IPs) onto the given heterogeneous NoC architecture so as to obtain the maximum throughput as well as to optimize the energy dissipation of whole system. Finally, the three differently heterogenous Tree-based network topologies are proposed as the NoC architectures for the study case of H.264 Decoder. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic powers of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and energy consumptions.