K. Baert

Linear and nonlinear optical properties of colloidal photonic crystals.

Linear and Nonlinear Optical Properties of Colloidal Photonic Crystals Luis Gonz alez-Urbina, Kasper Baert, Branko Kolaric,* Javier P erez-Moreno, and Koen Clays* Department of Chemistry and INPAC Institute of Nanoscale Physics and Chemistry, K. U. Leuven, Celestijnenlaan 200D, B-3001 Heverlee, Belgium Laboratoire Interfaces et Fluides Complexes, Centre d’Innovation et de Recherche en Mat eriaux Polym eres, Universit e de Mons, 20 Place du Parc, 7000 Mons, Belgium

Mechanical and electrical characterization of BCB as a bond and seal material for cavities housing (RF-)MEMS devices

This paper reports on the mechanical and electrical characterization of benzo-cyclo-butene (BCB) as a bonding and sealing material for 0-level packages (cavities) housing (RF-)MEMS devices. Shear strength and hermeticity of BCB-sealed cavities are experimentally investigated as functions of the geometrical parameters of the BCB sealing ring and the bonding conditions. The leak rate of BCB-sealed cavities strongly depends on the BCB width, and leak rates as low as 10−11 mbar l s−1 are measured for large BCB widths (>800 µm), dropping to 10−8 mbar l s−1 for BCB widths of around 100 µm. Depending on the bonding conditions, shear strengths as high as 150 MPa are achieved. BCB is also used in 0-level packaging of RF-MEMS devices, such as RF-switches and coplanar waveguides (CPWs). The electrical influence of the 0-level package is studied for different capping materials. It is experimentally shown that a 0-level package using capping chips made of low-loss high-resistivity materials (AF45 glass and high-resistivity silicon) and having a cavity height larger than about 45 µm above RF-MEMS devices, has a negligible impact on the microwave characteristics of an RF-MEMS device. Finally, some reliability testing is performed on BCB-sealed 0-level packages in order to study the influence of temperature and humidity on the mechanical properties of BCB. After testing in relatively harsh conditions, the BCB seal stays gross leak tight and shear strengths as high as 30 MPa are measured. BCB turns out to be a very robust and reliable material to encapsulate MEMS devices.

Sloped Through Wafer Vias for 3D Wafer Level Packaging

Through silicon via (TSV) technology is one of the critical and enabling technologies for 3D chip stacking. Many TSV approaches that have been demonstrated are application specific; and there is a great need for generic solutions. This work describes the design, fabrication and characterization of a TSV technology for silicon substrates where the interconnects are fabricated typically after standard CMOS processing and can be applied to any silicon based technology. This so-called 3D Wafer Level Packaging (3D-WLP) technology die stacking is based on a the thinning first, via last approach: the via is fabricated from the backside of a thinned wafer. Plasma etching of the wafer is used to achieve sloped profde which allows the conformal deposition of the dielectric layer and copper seed metallization. The vias are isolated from the substrate using polymer dielectrics; and spray coating of photoresist is used to pattern the dielectric within the vias. Electrical connection between the front and the back of the wafer is achieved by partial filling of the vias with copper. All processes employed in the fabrication of sloped through wafer vias are performed using standard wafer handling and at low temperature (< 250degC) for post CMOS compatibility. Various dimensions of TSVs are fabricated and electrically characterized by four point measurements. The measurements and calculations on daisy chains connecting a number vias in series show that the via resistance is in the range of 20-30mOmega depending on the via size. We believe that this generic 3D-WLP via approach is suitable for many 3D applications.

Comparative modelling for vibration scavengers [MEMS energy scavengers]

Conversion of the mechanical energy stored in vibrations into useful electrical energy is possible using three principles: electromagnetic, electrostatic and piezoelectric conversion. In order to build the appropriate device for a given application, a unifying model is proposed for these three principles. A methodology for comparison is presented based on this model in order to match the generator type to the input specifications (frequency, amplitude) and to the requirements at the electrical output, such as load impedance and voltage.

Nanoscaled interdigitated electrode arrays for biochemical sensors

Nanoscaled interdigitated electrode arrays were made with Deep U.V. lithography. Electrode widths and spacings from 500 nm down to 250 nm were achieved on large active areas (0.5 mm/spl times/1 mm). These electrodes allow for the detection of affinity binding of biomolecular structures (e.g. antigens, DNA) by impedimetric measurements. Such a sensor is developed, theoretically analyzed, experimentally characterized, and is demonstrated as an affinity biosensor.

Thin-film boron-doped polycrystalline silicon70%-germanium30% for thermopiles

Abstract CMOS-compatible thermopiles can be made by using the available polysilicon layer and aluminium layer as a thermocouple. SiGe would, however, offer a better performance than silicon, mostly due to its much lower thermal conductivity, while it maintains CMOS compatibility. The figure of merit of a highly boron doped (about 10 20 atoms cm −3 ) thin-film poly-Si 70% Ge 30% layer deposited by ultra-low-pressure chemical vapour deposition (ULPCVD) is reported. The figure of merit is measured with a dedicated structure: the Seebeck coefficient is ± 75 μ V K −1 , the thermal conductivity is ± 4.8 W mK −1 and the electrical resistivity is 23 μΩ m. The figure of merit is then calculated to be z ≈ 50 × 10 −6 K −1 .

Development of vertical and tapered via etch for 3D through wafer interconnect technology

Two types of dry silicon etch techniques are developed to cover two different areas of demand for interconnect technology: one for high aspect ratio (AR) vertical vias and one for tapered vias. Various sizes of vertical vias and trenches with diameters/widths ranging from 1-100 mum with an AR up to 50 are realized using Bosch deep reactive ion etch (DRIE) process. A linear model is applied to describe and to give physical insight in the aspect ratio dependant etch (ARDE) effect. The feasibility of the vertical vias as electrical interconnect is shown by isolating them from the substrate by silicon oxide and then filling with polysilicon. The tapered vias are typically post-processed on fabricated device wafers, making it inherently a more generic approach where diameter size can be large and low AR can be tolerated. Vias with a depth of ~100 mum and a diameter of ~50mum at the bottom (though larger at top) are realized. Varying various etch parameters, slope angles of 70deg-80deg are realized to allow for conformal deposition of dielectric/seed materials on the sidewalls and to allow lithography within the via. Reactive ion etch (RIE) is used to fabricate sloped vias by simultaneously applying etch and passivation gasses. Negative angles on the via top and sidewall roughness are observed that introduce conformal coating problems and increased leakage currents. Smoothening techniques using maskless wet and dry silicon etching are investigated to overcome these problems.

Spectral narrowing of emission in self-assembled colloidal photonic superlattices

We report on the influence of a well-designed passband in the stop band of a suitably engineered self-assembled colloidal photonic crystal superlattice on the steady-state emission properties of infiltrated fluorophores. The photonic superlattice was built by convective self-assembly of slabs of silica spheres of two different sizes. Transmission experiments on the engineered photonic crystal structure show two stop bands with an effective passband in between. The presence of this passband results in a narrow spectral range of increased density of states for photon modes. This shows up as a decrease in the emission suppression (enhancement of the emission) in the narrow effective passband spectral region. These experiments indicate that the threshold for lasing can possibly be lowered by spectrally narrowing the emission of fluorophores infiltrated in suitably engineered self-assembled photonic crystal superlattices, and are therefore important towards the realization of efficient all-optical integrated c...

Substrate bonding techniques for CMOS processed wafers

Transferring a CMOS circuit to a foreign substrate can be accomplished by bonding a processed silicon wafer to the substrate and subsequently thinning the silicon wafer. This paper presents both anodic bonding and adhesive bonding and evaluates their potential for circuit transfer.

Novel high growth rate processes for depositing poly-SiGe structural layers at CMOS compatible temperatures

This paper describes two novel processes for depositing poly-SiGe films at CMOS-compatible temperatures (/spl les/450/spl deg/C). A range of deposition temperatures is investigated to ensure compatibility with different CMOS generations. While the multilayer process investigates temperatures ranging between 420-450/spl deg/C, the microcrystalline SiGe deposition has been made possible at temperatures as low as 300/spl deg/C. These films are optimized to obtain low stress and stress gradient values suitable for MEMS structural layers. Low SiGe-Al contact resistivity on the order of 10/sup -7/ /spl Omega/.cm/sup 2/ and film resistivity as low as 1 m/spl Omega/.cm were achieved as well.