K. Ben Ali

Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates

Substrate crosstalk into standard and trap-rich high resistivity silicon (HR-Si) substrates over a wide frequency range, from ultralow frequency (ULF) to extremely high-frequency band (EHF), is investigated using finite-element numerical simulations and experiments. It is demonstrated that low-frequency substrate crosstalk is strongly impacted by the presence of free carriers at the interface between the HR-Si substrate and the interconnection passivation layers. The efficiency of a trap-rich layer, a polysilicon layer thicker than 300 nm, placed at that inter face to recover the nominal high-resistivity characteristic of the Si substrate is theoretically and experimentally demonstrated. Finally, the wideband crosstalk behavior of the HR-Si substrate with and without a trap-rich layer is modeled by means of a simple equivalent lumped-element circuit. The proposed model shows excellent agreement with finite-element numerical simulations and experimental data for frequencies above 100 kHz. Due to the introduction of a trap-rich layer, HR-Si substrate behaves as a lossless dielectric substrate. In that case, a purely capacitive electrical equivalent circuit is sufficient to properly describe the substrate crosstalk characteristics.

Porous Si as a substrate material for RF passive integration

Thick porous Si layers locally formed on a low resistivity Si wafer were studied for their application in on-chip RF device integration. A comparison was made between the above porous Si substrate and trap-rich high resistivity Si (trap-rich HR Si), which constitutes a state-of-the-art substrate for RF integration, by integrating identical co-planar waveguide transmission lines (CPW TLines) on both porous Si layer/low resistivity Si and trap-rich high resistivity Si. It was showed that signal attenuation on the porous Si layer is 30% lower than on trap-rich HR Si. This suggests lower losses or better RF shielding in the case of porous Si. In addition, CPW TLines were designed and realized on porous Si substrate for the frequency range 1-110GHz. The measured attenuation constant at 60 and 110GHz was respectively 0.33 and 0.55 dB/mm. This result competes very well with the best literature results on CMOS integrated transmission lines, even though the metal lines in the case of the porous Si substrate were not optimized.

Noise coupling between TSVs and active devices: Planar nMOSFETs vs. nFinFETs

Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port S-parameter measurements up to 40 GHz. The measurements clearly show that nFinFETs have better noise coupling immunity than planar nNMOSFETs. The dominant coupling mechanisms were also identified for both types of active devices. Moreover, calibrated TCAD models were developed. We show that via-last TSV architectures with thick liners (“donut TSVs”) and scaled TSV diameters reduce the noise coupling to active devices. Finally, both coupling and stress induced saturation current variations as a function of TSV to active devices distance were investigated. This allows us to propose a novel model for the TSV Keep Out Zone (KOZ) including electromagnetic coupling effects.

The effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devices

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer.

Through silicon via to FinFET noise coupling in 3-D integrated circuits

High speed TSV signals can penetrate through the dielectric liner material, transfer in the silicon substrate and degrade the performance of FEOL devices. In this paper we investigate TSV noise coupling to active device including both FinFET and planar transistors. Calibrated TCAD models are used to perform time domain analysis and understand the mechanisms of substrate noise interaction with active device. Parametric simulations are performed in order to understand the tradeoffs among different design parameters. The results demonstrate superior substrate noise immunity of FinFETs over equivalent planar transistors. In addition we show that a scaled TSV diameter, a novel TSV architecture with thick polymer liner, placing the substrate contact closer to active device and a TSV guard ring helps to mitigate the TSV noise. Finally the importance of electromagnetic coupling effects on Keep Out Zone (KOZ) extraction is illustrated.

Single event effects and total ionising dose in 600V Si-on-SiC LDMOS transistors for rad-hard space applications

This work presents a novel Si-on-SiC laterally-diffused (LD) MOSFET structure intended to provide high breakdown voltage of 600 V and be resistant for harsh-environment space applications. Single-event effects (SEE) and total ionizing dose (TID) are investigated for the first time in such device. Initially, the considered Si LDMOS structure on SiC suffers from single-event burnout (SEB) at a drain voltage > 175 V, i.e. much lower than the target. An optimized LDMOS structure with a heavily doped extended P+ buried region is proposed and shown to be SEB resistant at the target drain voltage of 600 V, even for a highly-energetic ion with a linear energy transfer (LET) of 90 MeV/mg/cm2. TID simulations indicate that the main concern is the charge build-up in the thick field oxide (FOX). FOX positive charge density beyond 1×1011 cm−2 causes the breakdown voltage to drop below 200 V. Different oxide types which feature low “net” positive charge build-up have to be considered to allow for higher TID hardness. The proposed Si/SiC structure with a p+ region was shown to be resistant to a combined SEE and TID (in case of limited positive charge build-up in FOX) as well as combined SEE and high-temperature (up to 573 K) environments. In comparison to the equivalent Silicon-on-Insulator (SOI) LDMOS, the Si/SiC LDMOS structure with p+ buried region features similar immunity to SEB but allows for higher TID hardness.

Nonlinear characteristics and RF losses of CPW and TFMS lines over a wide temperature range

This paper analyzes RF losses and non-linear behavior from room temperature up to 175°C of coplanar waveguide (CPW) and thin film microstrip (TFMS) lines fabricated on both High Resistivity (HR) and Standard resistivity (STD) Silicon-on-Insulator (SOI) substrates. Through measurements it is shown that CPW topology exhibits larger 2nd harmonic distortion level, more than 25 dB higher compared with TFMS counterpart at 25°C, whereas the later shows larger insertion losses. At higher temperature, RF losses increase for both transmission line topologies whereas the 2nd and 3rd harmonic levels are almost not affected by the temperature increase.