C. Roda Neve

Identification of RF Harmonic Distortion on Si Substrates and its Reduction Using a Trap-Rich Layer

Harmonic distortion (HD) is measured arising from coplanar waveguide structures on various substrates at 900 MHz, and significant distortion for silicon substrates is demonstrated for the first time. For an input power of +35 dBm, 2nd harmonic power of -47 dBm and 3rd of -57 dBm are measured for a thru calibration structure on oxidized high-resistivity silicon (HRS) substrates, and 2nd harmonic of -23 and 3rd of -20 dBm for a longer line on a thinner oxide. These levels are high compared to a full cellular transmit switch product specification of -45 and -40 dBm for 2nd and 3rd harmonics, respectively, at similar power levels. The contribution of the silicon substrate to high harmonic levels is investigated experimentally, and an efficient technological solution based on the introduction of a trap-rich layer is demonstrated.

RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates

In this paper, the nonlinear behavior of coplanar waveguide (CPW) transmission lines fabricated on Si and high-resistivity (HR) Si substrates is thoroughly investigated. Simulations and experimental characterization of 50- Ω CPW lines are analyzed under small- and large-signal operation at 900 MHz for a wide variety of Si substrates with nominal resistivities from 10 Ω-cm up to values higher than 10 kΩ-cm. The introduction of a trap-rich layer to recover the Si substrate nominal HR characteristics is also considered. We experimentally demonstrate that the distortion level of a CPW line lying on Si substrate decreases with the effective resistivity sensed by the coplanar structure. Si substrates of effective resistivity higher than 3 kΩ-cm present harmonic levels below -80 dBm for an output power of +15 dBm.

Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates

Substrate crosstalk into standard and trap-rich high resistivity silicon (HR-Si) substrates over a wide frequency range, from ultralow frequency (ULF) to extremely high-frequency band (EHF), is investigated using finite-element numerical simulations and experiments. It is demonstrated that low-frequency substrate crosstalk is strongly impacted by the presence of free carriers at the interface between the HR-Si substrate and the interconnection passivation layers. The efficiency of a trap-rich layer, a polysilicon layer thicker than 300 nm, placed at that inter face to recover the nominal high-resistivity characteristic of the Si substrate is theoretically and experimentally demonstrated. Finally, the wideband crosstalk behavior of the HR-Si substrate with and without a trap-rich layer is modeled by means of a simple equivalent lumped-element circuit. The proposed model shows excellent agreement with finite-element numerical simulations and experimental data for frequencies above 100 kHz. Due to the introduction of a trap-rich layer, HR-Si substrate behaves as a lossless dielectric substrate. In that case, a purely capacitive electrical equivalent circuit is sufficient to properly describe the substrate crosstalk characteristics.

RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer

In this paper we aim at comparing the static and RF performances of passive and active fully-depleted (FD) SOI MOSFETs fabricated on top of either a standard or a trap-rich HR-SOI UNIBOND wafer both provided by SOITEC.

Impact of Si substrate resistivity on the non-linear behaviour of RF CPW transmission lines

Non-linear behaviour of RF coplanar transmission lines is analyzed for various values of Si substrate resistivitiy. Based on small-signal measurements performed under different DC bias conditions, voltage dependent capacitance and conductance per unit length of the transmission line are extracted and compared for several silicon substrates. Harmonic distortion of large RF signal at 900 MHz along CPW lines is measured using a spectrum analyzer based setup as well as with a LSNA which gives us access to the phase of the harmonic components. For an input power of +25 dBm, the highest harmonic component (2nd) is as high as -15, -57, -37 and -63 dBm for resistivity substrates of 20, 500, 5 k and 2 kΩ-cm, respectively. A reduction of 45 and 15 dB for all harmonic components was obtained for the 5 and 2 kΩ-cm HR-Si substrates, respectively, when a trap-rich passivation layer was used at the Si/SiO2 interface, and for both characterization setups. The impact of the resistivity value on signal distortion with its relation to the bias-dependence substrate characteristic and the efficiency of the trap mechanism of the passivation layer are for the first time introduced from experimental result considerations.

Porous Si as a substrate material for RF passive integration

Thick porous Si layers locally formed on a low resistivity Si wafer were studied for their application in on-chip RF device integration. A comparison was made between the above porous Si substrate and trap-rich high resistivity Si (trap-rich HR Si), which constitutes a state-of-the-art substrate for RF integration, by integrating identical co-planar waveguide transmission lines (CPW TLines) on both porous Si layer/low resistivity Si and trap-rich high resistivity Si. It was showed that signal attenuation on the porous Si layer is 30% lower than on trap-rich HR Si. This suggests lower losses or better RF shielding in the case of porous Si. In addition, CPW TLines were designed and realized on porous Si substrate for the frequency range 1-110GHz. The measured attenuation constant at 60 and 110GHz was respectively 0.33 and 0.55 dB/mm. This result competes very well with the best literature results on CMOS integrated transmission lines, even though the metal lines in the case of the porous Si substrate were not optimized.

Efficient polysilicon passivation layer for crosstalk reduction in high-resistivity SOI substrates

Substrate crosstalk and RF losses in HR-SOI, and the introduction of a stabilized polysilicon layer are deeply investigated. A new equivalent lumped circuit to model different substrate types and resistivities, and SiO2-Si interface qualities is proposed and validated by simulation and experimental data. It is also valid to model the introduction of high-trap density at the interface, and it successfully explains the higher measured values of substrate crosstalk at low frequencies for HR-Si substrates.

Optical crosstalk reduction using a HR-si substrate with trap-rich passivation layer

The efficiency of a coplanar waveguide photo- induced Radio Frequency switch on a High Resistivity Silicon substrate is presented. Experimental results from 40 MHz to 40 GHz demonstrate the important reduction of transmission line losses and optical crosstalk obtained by introducing a trap-rich passivation layer (crystallized amorphous silicon) at the interface between the high resistivity silicon substrate and the field oxide.

Impact of neutron irradiation on oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer

This work investigates the influence of high-energy neutrons on oxidized high-resistivity Si substrates. Two oxide thicknesses as well as the presence of a trap-rich passivation layer are considered. The impact of neutron irradiation is directly related to the competition between the generation of interface traps, which are beneficial to reduce parasitic surface conduction (PCS) into the Si substrate similarly to the passivation layer, and accumulation of radiation induced positive charges in oxide, which would unfortunately increase PSC. It is shown that under neutron irradiation, RF losses are strongly reduced in the case of thin oxide, while substrates with a polysilicon passivation layer are almost insensitive to the neutron irradiation.

Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer

This work investigates the influence of high-energy neutrons on oxidized high-resistivity silicon substrates (HR-Si). Two oxide thicknesses as well as the presence of a trap-rich passivation layer are considered. The impact of neutron irradiation is directly related to the competition between the generation of interface traps added to the mobility and carrier lifetime degradation, which are beneficial to reduce parasitic surface conduction (PCS) into the Si substrate similarly to the passivation layer, and accumulation of radiation-induced positive charges in oxide, which would unfortunately increase PSC. It is shown that under neutron irradiation, RF losses are strongly reduced in the case of thin oxide (tox = 50 nm), while substrates with a polysilicon passivation layer are almost insensitive to the neutron irradiation.