J.-P. Raskin

RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates

In this paper, the nonlinear behavior of coplanar waveguide (CPW) transmission lines fabricated on Si and high-resistivity (HR) Si substrates is thoroughly investigated. Simulations and experimental characterization of 50- Ω CPW lines are analyzed under small- and large-signal operation at 900 MHz for a wide variety of Si substrates with nominal resistivities from 10 Ω-cm up to values higher than 10 kΩ-cm. The introduction of a trap-rich layer to recover the Si substrate nominal HR characteristics is also considered. We experimentally demonstrate that the distortion level of a CPW line lying on Si substrate decreases with the effective resistivity sensed by the coplanar structure. Si substrates of effective resistivity higher than 3 kΩ-cm present harmonic levels below -80 dBm for an output power of +15 dBm.

RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer

In this paper we aim at comparing the static and RF performances of passive and active fully-depleted (FD) SOI MOSFETs fabricated on top of either a standard or a trap-rich HR-SOI UNIBOND wafer both provided by SOITEC.

Impact of Si substrate resistivity on the non-linear behaviour of RF CPW transmission lines

Non-linear behaviour of RF coplanar transmission lines is analyzed for various values of Si substrate resistivitiy. Based on small-signal measurements performed under different DC bias conditions, voltage dependent capacitance and conductance per unit length of the transmission line are extracted and compared for several silicon substrates. Harmonic distortion of large RF signal at 900 MHz along CPW lines is measured using a spectrum analyzer based setup as well as with a LSNA which gives us access to the phase of the harmonic components. For an input power of +25 dBm, the highest harmonic component (2nd) is as high as -15, -57, -37 and -63 dBm for resistivity substrates of 20, 500, 5 k and 2 kΩ-cm, respectively. A reduction of 45 and 15 dB for all harmonic components was obtained for the 5 and 2 kΩ-cm HR-Si substrates, respectively, when a trap-rich passivation layer was used at the Si/SiO2 interface, and for both characterization setups. The impact of the resistivity value on signal distortion with its relation to the bias-dependence substrate characteristic and the efficiency of the trap mechanism of the passivation layer are for the first time introduced from experimental result considerations.

Porous Si as a substrate material for RF passive integration

Thick porous Si layers locally formed on a low resistivity Si wafer were studied for their application in on-chip RF device integration. A comparison was made between the above porous Si substrate and trap-rich high resistivity Si (trap-rich HR Si), which constitutes a state-of-the-art substrate for RF integration, by integrating identical co-planar waveguide transmission lines (CPW TLines) on both porous Si layer/low resistivity Si and trap-rich high resistivity Si. It was showed that signal attenuation on the porous Si layer is 30% lower than on trap-rich HR Si. This suggests lower losses or better RF shielding in the case of porous Si. In addition, CPW TLines were designed and realized on porous Si substrate for the frequency range 1-110GHz. The measured attenuation constant at 60 and 110GHz was respectively 0.33 and 0.55 dB/mm. This result competes very well with the best literature results on CMOS integrated transmission lines, even though the metal lines in the case of the porous Si substrate were not optimized.

Low power 23-GHz and 27-GHz distributed cascode amplifiers in a standard 130nm SOI CMOS process

Two fully integrated distributed amplifiers (DA) were designed using a standard 130 nm partially-depleted silicon-on-insulator CMOS process. They make use of either body-contacted (BC) or floating-body (FB) MOSFETs, and microstrip lines. The BC-DA has a 5.4 dB gain and a unity-gain bandwidth of 23 GHz whereas the FB-DA has a 6.8 dB gain and a unity-gain bandwidth of 27 GHz. The measured output power at 1 dB compression is 5 dBm at 5 GHz and the noise figure is 6.5-7.5 dB over 6-18 GHz for both DAs. Power consumption is 58 mW at 1.4 V.

Noise coupling between TSVs and active devices: Planar nMOSFETs vs. nFinFETs

Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port S-parameter measurements up to 40 GHz. The measurements clearly show that nFinFETs have better noise coupling immunity than planar nNMOSFETs. The dominant coupling mechanisms were also identified for both types of active devices. Moreover, calibrated TCAD models were developed. We show that via-last TSV architectures with thick liners (“donut TSVs”) and scaled TSV diameters reduce the noise coupling to active devices. Finally, both coupling and stress induced saturation current variations as a function of TSV to active devices distance were investigated. This allows us to propose a novel model for the TSV Keep Out Zone (KOZ) including electromagnetic coupling effects.

Modeling the effect of charges in the back side passivation layer on through silicon via (TSV) capacitance after wafer thinning

Evaluating the importance of electromagnetic (EM) coupling from through silicon vias (TSVs) has become crucial to the design of three-dimensional integrated circuits (3D-ICs). One of the most important parasitic contributions to signal propagation in 3D-ICs is the TSV capacitance. It is both frequency and bias dependent since a TSV is a metal-oxide-semiconductor (MOS) structure. In this work, anomalous TSV capacitance behavior after wafer thinning is reported and investigated by combining measurements and finite element (FEM) semiconductor simulations. Excellent agreement between models and experimental data confirms the origin of the anomalous TSV capacitance behavior: the presence of fixed charges in the back side (BS) passivation layer of the TSV after wafer thinning. In addition, a BS inversion layer can act as a conductive channel between neighboring vias, increasing the capacitive coupling between TSVs. Calibrated equivalent circuit models of the TSV in contact with a BS inversion layer are proposed for the first time in the context of 3D integration and validated.

A 2-mW Power Consumption Low Noise Amplifier in PD SOI CMOS Technology for 2.4 GHz Applications

This paper reviews and analyzes a fully integrated low-noise amplifier (LNA) for low-power and narrow-band applications using a cascode inductive source degeneration topology, with a body contacted transistor in 130 nm partially depleted CMOS SOI technology. Thanks to the SOI technology, the LNA shows only 2 mW power consumption when power gain of 10 dB and a noise figure of 3.1 dB at 2.4 GHz are measured for 1.2 V supply voltage

Design of a Distributed Amplifier with On-chip ESD Protection Circuit in 130 nm SOI CMOS Technology

A fully integrated common source distributed amplifier (CSDA) with ESD protection, designed and fabricated in 130 nm SOI CMOS technology, is presented. This CSDA requires a chip area of 0.75 mm2 . A gain of 4.5 dB and a unity-gain bandwidth of 30 GHz are measured at 1.4 V supply voltage with a measured power consumption of 66 mW. Low capacitance diode is used for electrostatic discharge (ESD) protection for the RF input pin without altering the original design of the CSDA. The CSDA has an ESD protection level up to 1.45 A transmission line pulse (TLP) current, corresponding to 2 kV human body model (HBM) stress

Optical crosstalk reduction using a HR-si substrate with trap-rich passivation layer

The efficiency of a coplanar waveguide photo- induced Radio Frequency switch on a High Resistivity Silicon substrate is presented. Experimental results from 40 MHz to 40 GHz demonstrate the important reduction of transmission line losses and optical crosstalk obtained by introducing a trap-rich passivation layer (crystallized amorphous silicon) at the interface between the high resistivity silicon substrate and the field oxide.