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Dive into the research topics where K. Croes is active.

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Featured researches published by K. Croes.


Microelectronics Reliability | 2001

A new degradation model and lifetime extrapolation technique for lightly doped drain nMOSFETs under hot-carrier degradation

R. Dreesen; K. Croes; Jean Manca; W. De Ceuninck; L. De Schepper; A Pergoot; G. Groeseneken

Abstract The hot-carrier degradation of lightly doped drain nMOSFETs is studied in detail. The degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The degradation behaviour of a characteristic MOSFET parameter is modelled over the complete degradation range, from 0.02 up to more than 10%. Furthermore, the introduction of a simultaneous non-linear least-square fit of the degradation curves has been successful for predicting the complete degradation behaviour at normal operating conditions.


Microelectronics Reliability | 1999

Modelling hot-carrier degradation of LDD NMOSFETs by using a high-resolution measurement technique

R. Dreesen; K. Croes; Jean Manca; W. De Ceuninck; L. De Schepper; A Pergoot; G. Groeseneken

Abstract By using a new, state-of-the-art measurement technique, the hot-carrier degradation of LDD nMOSFETs is studied. This high-resolution measurement technique, allows the measurement of degradation levels as low as 0.03 %. A new model based on Goo et al. [1] has been developed and verified in the full region between 0.03 up to almost 10 % for the ageing parameter I d,lin . The introduction of a simultaneous non-linear least-square fit of the degradation curves has been successful for predicting the complete degradation behaviour at real life operating conditions.


Applied Physics Letters | 2013

Correlation between field dependent electrical conduction and dielectric breakdown in a SiCOH based low-k (k = 2.0) dielectric

Chen Wu; Yunlong Li; Yohan Barbarin; Ivan Ciofi; K. Croes; Jürgen Bömmels; I. De Wolf; Zs. Tőkei

The electrical conduction of a SiCOH based ultralow-k (ku2009=u20092.0) dielectric is investigated over an electric field range from 1.0u2009MV/cm to breakdown. Below 4.0u2009MV/cm, space-charge-limited current dominates the leakage. Above 5.0u2009MV/cm, a transition is found from trap-assisted Fowler-Nordheim (F-N) tunneling to F-N tunneling. It is hypothesized that under F-N tunneling stress, intrinsic material degradation causes positively charged defects generated in the dielectric. Moreover, this change of the dominant conduction path has a significant impact on the time dependent dielectric breakdown lifetime behavior.


Microelectronics Reliability | 1998

The time of “guessing” your failure time distribution is over!

K. Croes; Jean Manca; W. De Ceuninck; L. De Schepper; G. Molenberghs

Abstract Each statistical analysis of reliability data starts with the choice of the underlying distribution of failure times. This choice is of great importance because all conclusions drawn from this analysis will depend on it. Lifetime predictions can vary orders of magnitude depending on the distribution used. Most researchers choose the underlying distribution of failure times rather unfounded: because of “historical” reasons, because everybody uses it,… We developed a method which offers reliability engineers an objective tool for making the distinction between the two most widely used distributions, the lognormal and the Weibull, using a statistical well-founded technique. Essentially, the method comes down to constructing both the lognormal and the Weibull probability plot of the data set under consideration. For each plot, the Pearsons correlation coefficient is calculated. It is shown that the ratio of these two correlation coefficients is a pivotal quantity. Hence, it can serve as a test statistic.


china semiconductor technology international conference | 2011

Evaluation of Metallization Options for Advanced Cu Interconnects Application

Nicolas Jourdan; L. Carbonell; Nancy Heylen; Johan Swerts; Silvia Armini; A. Maestre Caro; S. Demuynck; K. Croes; G. Beyer; Zsolt Tokei; S. Van Elshocht; Eric Vancoille

The traditional Cu interconnect barrier/seed process consisting of PVD-Ta based barrier/Cu-seed will reach its limit between 20 nm and 30 nm wide trench dimension. To extend Cu interconnect technology further, possible solutions such as PVD-RuTa, PEALD-Ru-based, CVD-Co, PVD/CVD-self-formed-MnSixOy and self-assembled monolayers (SAMs) are studied. It is shown that both PVD-RuTa and CVD-Co possess the so-called seed enhancement capability allowing Cu filling of narrow recesses. However, they exhibit limitations in terms of Cu-diffusion barrier efficiency, electromigration reliability and scalability. Despite, the concept of SAM [NH2-SAM(C3)] as Cu diffusion barrier is demonstrated, it requires maturity and compatibility within the process flow (e.g. adhesion with the Cu overlayer). Finally, it is considered that PEALD-Ru-based alloys and CVD-based MnSixOy films are serious candidates for sub-30 nm wide trench technologies because of their conformal nature and ability to act as an efficient Cu diffusion barrier in the range of 2 nm thickness.


Microelectronics Reliability | 2000

Reliability aspects of high temperature power MOSFETs

Jean Manca; Wolfgang Wondrak; W. Schaper; K. Croes; J. D’Haen; W. De Ceuninck; B. Dieval; Hans L. Hartnagel; Marc D'olieslaeger; L. De Schepper

Abstract Gate oxide reliability and thermal shock resistance of power MOSFETs for high temperature applications, have been investigated by accelerated tests and several analytical and electrical techniques. Thermal shock tests have been performed between -40°C and 200°C with subsequent electrical tests and failure analysis. Time Dependent Dielectric Breakdown (TDDB) of the gate oxide has been studied in detail by means of in-situ leakage current measurements at various voltages and temperatures.A statistical analysis of the results yields information on the underlying failure time distribution, failure mechanisms and lifetime.


Microelectronics Reliability | 2001

High-resolution in-situ of gold electromigration: test time reduction

K. Croes; R. Dreesen; Jean Manca; W. De Ceuninck; L. De Schepper; L. Tielemans; P.J. van der Wel

Mat Res Inst, B-3590 Diepenbeek, Belgium. Xpeqt, B-3980 Tessenderlo, Belgium. Philips Semicond, NL-6539 AE Nijmegen, Netherlands.Croes, K, Mat Res Inst, Wetenschapspk 1, B-3590 Diepenbeek, Belgium.


Journal of the American Society for Mass Spectrometry | 1999

Investigation of the formation of M 2 + -molecular ions in sputtering processes

Johan Vlekken; K. Croes; Ting-Di Wu; M. D’Olieslaeger; G. Knuyt; Wilfried Vandervorst; Luc De Schepper

The formation process of M2+ molecular ions sputtered from elementary target materials is investigated. In a previous article it was shown that these molecules can be used to quantitate major elements [1]. The quantitation method was based on the assumption that the M2+ molecular ions are formed by the atomic combination of independently sputtered M and M+ particles above the surface. In this paper this assumption will be investigated using a Monte Carlo model to simulate the formation mechanism. The model is used to calculate the velocity distribution of the M2+ dimers sputtered from three different elementary target materials (Fe, Ge, and Ni). The results are compared with experimental data. Good agreement exists between theory and experiment that supports the Monte Carlo model and hence also the assumed formation mechanism.


Quality and Reliability Engineering International | 1998

Bimodal failure behaviour of metal film resistors

K. Croes; W. De Ceuninck; L. De Schepper; L. Tielemans

The ageing behaviour of metal film resistors was studied using high-resolution in-situ resistance measurements. A temperature storage experiment was performed at five different temperature levels. At each condition, the ageing behaviour of 128 resistors was monitored. It turned out that the failure behaviour of the samples is rather complicated. One remarkable fact is that measurements coming from two different production lots led to completely different results. One production lot displayed monomodal failure behaviour, while for the other lot bimodality was observed. Serious errors in the calculation of the FTTF (first time to failure) can be expected when this fact is not properly taken into consideration. This paper also discusses some important aspects of the analysis of failure time data, such as (i) the choice of the underlying failure distribution, (ii) the number of samples to be tested and (iii) the failure criterion to be used.


2012 4th Electronic System-Integration Technology Conference | 2012

Thermal mismatch induced reliability issues for Cu filled through-silicon vias

Joke De Messemaeker; K. Croes; Bart Vandevelde; Dimitrios Velenis; Augusto Redolfi; Anne Jourdain; G. Beyer; Bart Swinnen; E. Beyne; Ingrid DeWolf

This paper reports on experiments assessing 3 potential impacts and reliability risks induced by the thermal mismatch between Cu and Si in Cu filled through-silicon via (TSV) integration in 3D technology. The results show that (1) the Cu stress is a higher contributor to stress in the Si than FEOL film edge effects induced by TSV etch; (2) Cu extrusion induced by BEOL processing does not lead to severe delamination/cracking in low-k BEOL layers above the TSV; (3) stress induced at the TSV bottom does not cause visible damage to the liner or backside passivation after wafer thinning.

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L. Tielemans

Katholieke Universiteit Leuven

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Wilfried Vandervorst

Katholieke Universiteit Leuven

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I. De Wolf

Katholieke Universiteit Leuven

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Jürgen Bömmels

Katholieke Universiteit Leuven

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