Jürgen Bömmels

The economic impact of EUV lithography on critical process modules

Traditionally, semiconductor density scaling has been supported by optical lithography. The ability of the exposure tools to provide shorter exposure wavelengths or higher numerical apertures have allowed optical lithography be on the forefront of dimensional scaling for the semiconductor industry. Unfortunately, the roadmap for lithography is currently at a juncture of a major paradigm shift. EUV Lithography is steadily maturing but not fully ready to be inserted into HVM. Unfortunately, there are no alternative litho candidates on the horizon that can take over from 193nm. As a result, it is important to look into the insertion point of EUV that would be ideal for the industry from an economical perspective. This paper details the benefit observed by such a transition. Furthermore, it looks into such detail with an EUV throughput sensitivity study.

Design Technology co-optimization for N10

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

DTCO at N7 and beyond: patterning and electrical compromises and opportunities

At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, designers can actively help by exploring scaling options that do not necessarily require aggressive pitch scaling. In this paper we will illustrate how MOL scheme and patterning can be optimized to achieve a dense SRAM cell; how optimizing device performance can lead to smaller standard cells; how the metal interconnect stack needs to be adjusted for unidirectional metals and how a vertical transistor can shift design paradigms. This paper demonstrates that scaling has become a joint design-technology co-optimization effort between process technology and design specialists, that expands beyond just patterning enabled dimensional scaling.

The need for EUV lithography at advanced technology for sustainable wafer cost

Extreme Ultra-Violet lithography (EUVL) is considered as the most promising candidate to replace optical lithography from the 14nm technology node onwards. EUVL has recently been supplanted by multiple patterning using existing 193nm immersion lithography tools for upcoming 14 nm technology node due to the current resolution limitations and production level efficiency restrictions. In this paper, a wafer cost model for technology node from 28nm down to 14nm has been developed. It identifies lithography module as the key component where innovation can be leveraged to reduce cost. The results presented in the paper reveal that wafer cost will be increased by 30% from 28nm to 20nm technology node. A 70% increase in wafer cost is foreseen during a transition from 20nm to 14nm node based on 193nm immersion lithography and multiple patterning. The cost analysis predicts a 30% wafer cost reduction by adapting EUVL at a 14 nm technology node compared to 193nm immersion technology (normalized to 28nm wafer cost). It proves that the readiness of EUVL is critical to keep scale the logic devices at the pace of Moore’s law without violating the scale of economics in semiconductor industry.

Enabling CD SEM metrology for 5nm technology node and beyond

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

Impact of process variability on BEOL TDDB lifetime model assessment

We investigate the impact of process variability on BEOL TDDB lifetime model assessment. The change in functional form of TDDB lifetime plots due to line-to-line variability and line-edge-roughness has been quantified in the field range in which long term TDDB measurements have been obtained. We found that the Pearson R2, which is used as a measure of linearity of a lifetime plot, did not significantly change due to process variability. Where process variability has a significant effect on TDDB and needs to be taken into account during data analysis, our simulations suggest that it does not have an impact on BEOL TDDB lifetime model assessment. We propose that the conclusions from recent literature reports which point in the direction of a less conservative model compared to the √E-model are valid, although they do not take process variability into account during the data analysis.

Intrinsic reliability of local interconnects for N7 and beyond

The intrinsic Time Dependent Dielectric Breakdown properties of the spacer between gate and first level local interconnects are assessed for dielectrics and spacings compatible with N7 and beyond. The intrinsic reliability properties down to 3nm thickness of standard LPCVD Si3N4- and PECVD Si3N4-films as well as more advanced Al2O3- and low-k CVD SiN-layers have been studied using imecs pcap test vehicle. It turned out that the leakage current of the more advanced films are not worse compared to the more standard layers. Besides, their reliability performance, in terms of Emax, is the same or even slightly better. Down to 3nm thickness, Emax-values higher than 3.5MV/cm were obtained for all dielectrics studied. Fundamental insight in the breakdown processes is obtained by testing a wide thickness range (3-20nm) for the PECVD Si3N4-layer, where higher Emax and QBD were found for the thinner layers, suggesting that less damage is created by electrons when injecting them into thinner films (fluence driven failure mechanism). A difference in leakage and reliability when applying different polarities suggests different mechanisms playing a role when the electrons are injected from the interconnect or from the gate metal. Finally, field simulations at critical locations in the studied structure were used to assess places of higher local field enhancement. We found that at these places, the fields were still lower compared to the Emax-values of the intrinsic films, suggesting that scalability down to 3nm spacer thickness is intrinsically reliable.

Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers

The semiconductor scaling roadmap shows the continuous node to node scaling to push Moore’s law down to the next generations. In that context, the foundry N5 node requires 32nm metal pitch interconnects for the advanced logic Back- End of Line (BEoL). 193immersion usage now requires self-aligned and/or multiple patterning technique combinations to enable such critical dimension. On the other hand, EUV insertion investigation shows that 32nm metal pitch is still a challenge but, related to process flow complexity, presents some clear motivations. Imec has already evaluated on test chip vehicles with different patterning approaches: 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization). Following the run path in the technology development for EUV insertion, imec N7 platform (iN7, corresponding node to the foundry N5) is developed for those BEoL layers. In this paper, following technical motivation and development learning, a comparison between the iArF SAQP/EUV block hybrid integration scheme and a single patterning EUV flow is proposed. These two integration patterning options will be finally compared from current morphological and electrical criteria.

Directed self-assembly enabled fully self-aligned via processing (Conference Presentation)

Until recent years, dimensional scaling allowed for the fabrication of smaller and faster devices with increasing capacity. Currently, the limited area and the high density of the features in such devices have made self-aligned contacts/vias (SAC or SAV) a standard technique to overcome the decreasing distance between electrically functional elements in integrated circuits. In SAV schemes, the use of hard masks to define the effective transferred patterns allows for more relaxed via patterning conditions and overlay requirements. In this work, we explore a DSA-based fully self-aligned vias (FSAV) flow to further improve on traditional SAV processes. We use directed self-assembly (DSA) of block copolymers (BCP) to generate topographic features between the metal lines, which in combination with SAV, extend the benefits of this method to both X-Y directions, while maximizing the distance between the contacts and the adjacent not-connected metal lines to avoid potential shorts, as shown in Figure 1. In order to achieve this, patterned metal and/or dielectric lines are selectively functionalized using homopolymer brushes, to form a 1:1 chemical nano-pattern of specific surface energy, such that, when a BCP layer is coated and annealed on these samples, each block will align to the metal (or dielectric) lines underneath, as shown on Figure 2. We subsequently use one of the blocks as a template to generate topographic features between the metal lines. In addition, different hard masks are characterized to find the optimal material for the current scheme. Finally, we define the design rules for integration of the proposed flow into electrical devices.