I. De Wolf

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

Micro-Raman study of stress distribution in local isolation structures and correlation with transmission electron microscopy

Stress in local isolation structures is studied by micro‐Raman spectroscopy. The results are correlated with predictions of an analytical model for the stress distribution and with cross‐sectional transmission electron microscopy observations. The measurements are performed on structures on which the Si3N4 oxidation mask is still present. The influence of the pitch of the periodic local isolation pattern, consisting of parallel lines, the thickness of the mask, and the length of the bird’s beak on the stress distribution are studied. It is found that compressive stress is present in the Si substrate under the center of the oxidation mask lines, with a magnitude dependent on the width of the lines. Large tensile stress is concentrated under the bird’s beak and is found to increase with decreasing length of the bird’s beak and with increasing thickness of the Si3N4 film.

Analytical Model of the DC Actuation of Electrostatic MEMS Devices With Distributed Dielectric Charging and Nonplanar Electrodes

This paper gives a new insight into the problem of the irreversible stiction of RF microelectromechanical systems (MEMS) attributed to the dielectric charging. We present a model for the electrostatic actuation of MEMS devices taking into account the nonuniform distributions of the air gap and the charges in the dielectric layer. The major result of our study is the impossibility to invoke the sole uniform dielectric charging phenomenon to explain the irreversible stiction of electrostatic MEMS devices. In the absence of other forces, a nonzero variance of the charge distribution is required to explain the stiction of the device. Considering only uniform residual charge densities, previous reported works could only account for a drift of the actuation characteristics as a whole. In case of a uniform air-gap distribution, our analytical model can already account for an increase of the up-capacitance, a shift of the - , its narrowing, and the stiction by a closure of the pull-out window. We further show that the combined nonuniformities of air gaps and charges break the symmetry of the actuation characteristics. The asymmetry can be such that one of the pull-in points disappears, which is replaced by a continuous tuning range while the other pull-in point still exists.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Stresses and strains in lattice-mismatched stripes, quantum wires, quantum dots, and substrates in Si technology

We discuss recent advances made in the theory and measurements of stresses and strains in Si‐based heterostructures containing submicron‐ and micron‐size features. Several reports on theoretical as well as experimental studies of stresses in the substrates with local oxidation of silicon structures on the surface have been published recently. With the advent of GeXSi1−X strained layers and stripes extensive studies of both the stripe and the substrate stresses have also been made. Unlike the previous calculations and analytical models, recent finite element (FE) calculations take into account the coupling between the film–substrate stresses without making the approximation that the interface is rigid or that there is no variation of stresses in the stripes in a direction perpendicular to the interface. The results of these calculations have been compared with the analytical models and limitations of the analytical models have been pointed out. Micro‐Raman measurements of the stresses in the stripes, quant...

Cu pumping in TSVs: Effect of pre-CMP thermal budget

Abstract When Cu ‘Through-Silicon-Vias’ (TSVs) are exposed to high temperatures as typically encountered during the back-end of line (BEOL) processing, the higher coefficient of thermal expansion (CTE) of Cu forces it to expand more than Si. This causes compressive stress in the confined Cu inside the TSV. This stress can partly be released near the top of the TSV, by out-of-plane expansion of the Cu, the so-called ‘Cu pumping’. It can severely damage the BEOL layers. In this paper the effect of a pre-CMP thermal budget (temperature and time) on Cu pumping is studied for various Cu chemistries and TSV aspect ratios. It is shown that to suppress Cu pumping a pre-CMP anneal is required that is either very long or at a temperature very close to the maximum temperature used in the BEOL processing.

Mechanical and electrical characterization of BCB as a bond and seal material for cavities housing (RF-)MEMS devices

This paper reports on the mechanical and electrical characterization of benzo-cyclo-butene (BCB) as a bonding and sealing material for 0-level packages (cavities) housing (RF-)MEMS devices. Shear strength and hermeticity of BCB-sealed cavities are experimentally investigated as functions of the geometrical parameters of the BCB sealing ring and the bonding conditions. The leak rate of BCB-sealed cavities strongly depends on the BCB width, and leak rates as low as 10−11 mbar l s−1 are measured for large BCB widths (>800 µm), dropping to 10−8 mbar l s−1 for BCB widths of around 100 µm. Depending on the bonding conditions, shear strengths as high as 150 MPa are achieved. BCB is also used in 0-level packaging of RF-MEMS devices, such as RF-switches and coplanar waveguides (CPWs). The electrical influence of the 0-level package is studied for different capping materials. It is experimentally shown that a 0-level package using capping chips made of low-loss high-resistivity materials (AF45 glass and high-resistivity silicon) and having a cavity height larger than about 45 µm above RF-MEMS devices, has a negligible impact on the microwave characteristics of an RF-MEMS device. Finally, some reliability testing is performed on BCB-sealed 0-level packages in order to study the influence of temperature and humidity on the mechanical properties of BCB. After testing in relatively harsh conditions, the BCB seal stays gross leak tight and shear strengths as high as 30 MPa are measured. BCB turns out to be a very robust and reliable material to encapsulate MEMS devices.

Influence of process-induced stress on device characteristics and its impact on scaled device performance

This paper reports on the effects of oxidation-induced stress on the generation current in pn-junction and gated diodes. It is observed that even in the regime where no extended defects are present, the generation current is a strong function of the compressive stress in the substrate. Experimental results are presented revealing an order of magnitude increase in generation current for stress changes of a few 100 MPas. A stress-induced bandgap narrowing model that describes the relationship between the oxidation-induced stress and the generation current in MOS devices is proposed and experimentally verified. Using this model, we have calculated the stress-induced generation current in scaled shallow trench isolated (STI) devices due to reoxidation after STI formation. As the device pitch is reduced a large increase in stress and leakage current is observed, consistent with the experimental data.

Process‐induced mechanical stress in isolation structures studied by micro‐Raman spectroscopy

Micro‐Raman spectroscopy is used to study mechanical stress in local isolation structures on silicon substrates (poly‐buffered local oxidation of silicon, called PBLOCOS or LOPOS). The influence of processing parameters such as nitride film thickness and width, pad oxide thickness, and field oxide thickness is studied. Also the change of the local stress during the successive processing steps of the isolation is investigated: deposition of the nitride mask, field oxidation, and removal of the nitride mask. The results are explained using a simple analytical model. It is found that stress varies very much during the different processing stages. After deposition of the nitride film, the stress is compressive under the mask lines and tensile outside the lines, close to the line border. The stress magnitude is highly dependent on the thickness of the nitride film. It can be described by edge forces. During field oxidation, this edge‐force‐induced stress nearly completely relaxes. In LOPOS structures with fiel...

Polyimide-Enhanced Stretchable Interconnects: Design, Fabrication, and Characterization

This paper discusses the optimization of a stretchable electrical interconnection between integrated circuits in terms of stretchability and fatigue lifetime. The interconnection is based on Cu stripes embedded in a polyimide-enhanced (PI-enhanced) layer. Design-of-experiment (DOE) methods and finite-element modeling were used to obtain an optimal design and to define design guidelines, concerning both stripe and layer dimensions and material selection. Stretchable interconnects with a PI-enhanced layer were fabricated based on the optimized design parameters and tested. In situ experimental observations did validate the optimal design. Statistical analysis indicated that the PI width plays the most important role among the different design parameters. By increasing the PI width, the plastic strain in the Cu stripes is reduced, and thus, the stretchability and fatigue lifetime of the system is increased. The experimental results demonstrate that the PI-enhanced stretchable interconnect enables elongations up to 250% without Cu rupture. This maximum elongation is two times larger than the one in samples without PI enhancement . Moreover, the fatigue life at 30% elongation is 470 times higher.