C. H. Tung

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

Ultrathin low temperature SiGe buffer for the growth of high quality Ge epilayer on Si(100) by ultrahigh vacuum chemical vapor deposition

The authors report a method to grow high quality strain-relaxed Ge on a combination of low-temperature Ge seed layer on low temperature ultrathin Si0.8Ge0.2 buffer with thickness of 27.3nm by ultrahigh vacuum/chemical-vapor-deposition method without the need to use chemical mechanical polish or high temperature annealing. On 8in. Si wafer, the etch-pit density was 6×106cm−2. The root-mean-square surface roughnesses of Ge epitaxy by atomic force microscopy were 1.4 and 1.2nm for bulk Si and silicon-on-insulator substrates, respectively. Micro-Raman spectroscopy shows extremely uniform distribution of residual strain in the overgrown Ge epitaxy on 8in. wafers.

The nature of dielectric breakdown

Dielectric breakdown is the process of local materials transiting from insulating to conductive when the dielectric is submerged in a high external electric field environment. We show that the atomistic changes of the chemical bonding in a nanoscale breakdown path are extensive and irreversible. Oxygen atoms in dielectric SiO2 are washed out with substoichiometric silicon oxide (SiOx with x<2) formation, and local energy gap lowering with intermediate bonding state of silicon atoms (Si1+, Si2+, and Si3+) in the percolation leakage path. Oxygen deficiency within the breakdown path is estimated to be as high as 50%–60%.

CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach

This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achieve symmetric pull-up and pull-down, sharp ON- OFF transitions with high voltage gains (e.g., DeltaV OUT/DeltaV IN up to ~ 40 for V DD = 1.2 V) are obtained. The inverter maintains its good transfer characteristics and noise margins for wide range of V DD tested down to 0.4 V. Individual transistors show excellent subthreshold characteristics and drive currents. The results are discussed in light of the circuit performances reported for other advanced nonclassical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS-circuit functionality is thus demonstrated.

Aluminum oxynitride interfacial passivation layer for high-permittivity gate dielectric stack on gallium arsenide

The authors demonstrate a passivation technique for GaAs substrate by employing an aluminum oxynitride (AlON) interfacial passivation layer. X-ray photoelectron spectroscopy and transmission electron microscopy results show that the AlON interfacial passivation layer effectively suppresses the formation of Ga or As oxide during the gate dielectric deposition process. This enabled the fabrication of high quality GaAs n-channel metal-oxide-semiconductor capacitors with HfO2 gate dielectric and TaN metal gate electrode. The metal gate/high-k gate dielectric stack on GaAs demonstrated an equivalent SiO2 thickness of 2.2nm and low leakage current density of 4.27×10−4A∕cm2 at a gate bias equal to Vfb−1V. Excellent capacitance-voltage characteristics with low frequency dispersion (∼4%) were also obtained.

Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

We present, for the first time, the monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. The drive currents for N-and P-MOS transistors are matched using different number of channels for each to obtain symmetric pull-up and pull-down characteristics. Sharp ON-OFF transitions with high voltage gains (up to -45) are obtained which are best reported among the nanowire and carbon nanotube inverters. The inverters maintain their good transfer characteristics and noise margins for a wide range of VDD values, down to 0.2 V. Short circuit current at 0.2 V VDD is ~6 pA indicating excellent potential of these devices for low voltage and ultra low power applications. These results excel those reported in the literature for nanowire as well as FinFET (non-classical CMOS) inverters.

Fabrication Aspects of Germanium on Insulator from Sputtered Ge on Si-Substrates

Germanium (Ge) metal-oxide-semiconductor-field-effect transistors (MOSFETs) have higher carrier mobilities than Si. We have studied the growth of high quality single-crystal germanium on insulator (GOI) using rapid liquid-phase epitaxial growth and defect-necking techniques. Stable single-crystal Ge growth was seen at a temperature of 925 °C, below the melting point of Ge. At and above the Ge melting temperature, we found Ge segregating into balls. Defect-free crystals were grown from the semisolid state of Ge. The defect-necking technique was improved with an underlying insulator undercut to minimize dislocation or stacking faults. Up to 60 μm long crystal-on-insulators were grown. Strain analysis of grown Ge was studied using Raman spectroscopy, and grown films were found to have tensile strain.

Epitaxially grown n-ZnO∕MgO∕TiN∕n+-Si(111) heterostructured light-emitting diode

Epitaxial n-ZnO∕MgO∕TiN∕n+-Si heterostructured light-emitting diodes have been fabricated. The epitaxial growth of MgO∕TiN on Si(111) was established by pulsed laser deposition, which was further employed as a buffer layer for epitaxial growth of ZnO layer by metal-organic chemical-vapor deposition. Good epitaxial quality was found using high-resolution x-ray diffraction and transmission electron microscopy. A strong wide electroluminescence band, ranging from 350to850nm and centered at ∼530nm, was observed from the diode when a positive voltage was applied on Si substrate. The diode exhibited a linear light-output-current characteristic with an injection current up to 192mA.

The radial distribution of defects in a percolation path

Our results show that the defect distribution within a nanometer size percolation path is nonuniform. The defects, which are shown as oxygen vacancies, spread out radially from the center of the percolation path. The conduction band edges of the defective oxide are lowered for 0.14–0.78eV when the Si–O composition changes from SiO1.76 to SiO0.7.

Dielectric breakdown induced epitaxy in ultrathin gate oxide - a reliability concern

Breakdowns in ultrathin gate oxide (Gox) ranging from 16-33 /spl Aring/ were physically analyzed with transmission electron microscope after constant voltage stress. In the Gox of 25 and 33/spl Aring/, a dielectric breakdown induced epitaxy (DBIE) at the gate oxide region is detected for compliance current of 100 nA and above, regardless of breakdown hardness. The compliance current for the transition of soft breakdown (SBD) to hard breakdown (HBD) is found to be in the range of 10-100 /spl mu/A, whereas for the thinner Gox of 16 /spl Aring/, the upper compliance current limit of SBD to HBD is greatly reduced to around 1 - 10 /spl mu/A and SBD DBIE is hardly detected. The results clearly indicate that DBIE is always present in the HBD oxides regardless of its thickness. Its presence in the SBD oxides is an indication of the early stage of catastrophic failure process that poses a Gox reliability concern.