Sanjeev Aggarwal

Reliability properties of low-voltage ferroelectric capacitors and memory arrays

We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.

Stoichiometry and phase purity of Pb(Zr,Ti)O3 thin films deposited by metal organic chemical vapor deposition

(Pb,Zr)TiO3 (PZT) films have been prepared by metal organic chemical vapor deposition on 200mm wafers. Phase pure perovskite films were deposited in a self-correcting region where the Pb stoichiometry is relatively insensitive to increasing Pb content in the gas phase. Films deposited with Pb flows lower than those used in the self-correcting region showed second phase ZrO2 whereas films deposited at Pb flows higher than those used in the self-correcting region showed second phase PbO. The PZT grains are columnar, extending from the bottom electrode to the top electrode. In the self-correcting region, PZT films of 70nm nominal thickness show good ferroelectric behavior with switched polarization of ∼40μC∕cm2 at 1.5V and saturation voltage of ∼1.2V. The films have an average roughness of ∼4nm with grain size of ∼700A. The impact of the deposition parameters such as deposition temperature, pressure, precursor flow, and oxygen flow during deposition on the self-correcting region was investigated. Increasing ...

Embedded ferroelectric memory using a 130-nm 5 metal layer Cu / FSG logic process

An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu / FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution of small ferroelectric capacitors (< 0.2 /spl mu/m/sup 2/) was measured after fabrication and bake. A reasonable amount of property degradation after 6000hr 125/spl deg/C bake was observed.

Plasma Etch Processes for Embedded FRAM Integration

We describe the etch processes used for integration of embedded ferroelectric random access memory (FRAM) within a standard CMOS logic flow. The ferroelectric module is inserted following front-end contact formation and prior to backend integration using only two additional mask levels: capacitor pattern and bi-level via pattern. The single-mask stack etch process employs a TiAlN hardmask to define Ir/IrOx/PZT/IrOx/Ir capacitors. Protective sidewalls can be formed using an etchback process. The bi-level via etch and subsequent metal fill processes complete the FRAM module formation. Functional 4 MB arrays embedded with 5 levels of Cu/FSG integration have been demonstrated.

Integration and bit distribution of production-worthy FRAM embedded with 130nm CMOS logic

High density embedded FRAM has been fabricated within a 130nm, 5LM Cu/FSG CMOS logic process with only two additional masks. Integrated arrays, fabricated with 70nm-thick MOCVD lead zirconate titanate (PZT) as the ferroelectric and Ir/IrO2 electrodes, show good separation voltage and wide signal margin between the two data states. Ferroelectric processing does not adversely affect the CMOS properties. Opposite state retention measurements of the arrays project greater than 10 years lifetime at 85degC