K. Shenai

Optimum semiconductors for high-power electronics

Elemental and compound semiconductors, including wide-bandgap semiconductors, are critically examined for high-power electronic applications in terms of several parameters. On the basis of an analysis applicable to a wide range of semiconducting materials and by using the available measured physical parameters, it is shown that wide-bandgap semiconductors such as SiC and diamond could offer significant advantages compared to either silicon or group III-V compound semiconductors for these applications. The analysis uses peak electric field strength at avalanche breakdown as a critical material parameter for evaluating the quality of a semiconducting material for high-power electronics. Theoretical calculations show improvement by orders of magnitude in the on-resistance, twentyfold improvement in the maximum frequency of operation, and potential for successful operation at temperatures beyond 600 degrees C for diamond high-power devices. New figures of merit for power-handling capability that emphasize electrical and thermal conductivities of the material are derived and are applied to various semiconducting materials. It is shown that an improvement in power-handling capabilities of semiconductor devices by three orders of magnitude is feasible by replacing silicon with silicon carbide; improvement in power-handling capability by six orders of magnitude is projected for diamond-based devices. >

Performance evaluation of high-power wide band-gap semiconductor rectifiers

Applicability of GaN in unipolar and bipolar devices for high-power electronic applications is evaluated with respect to similar devices based on other materials. Specific resistance is used as a measure of unipolar performance. In order to evaluate bipolar performance, 700 and 6000 V p-i-n diodes based on Si, 6H-SiC, and GaN are compared with respect to forward conduction and reverse recovery performance at room temperature and high-temperature conditions. It is shown that GaN is advantageous not only for high voltage unipolar applications, but also for bipolar applications. An empirical closed-form expression is presented to predict the avalanche breakdown voltage of wide band-gap semiconductors. Formulation of the expression is based on an approximation of the impact ionization coefficient in terms of seventh power of the electric field.

Current transport mechanisms in atomically abrupt metal-semiconductor interfaces

A comprehensive model for electron transport mechanisms across a fully formed Schottky-barrier junction is proposed in which the metal-semiconductor interface is approximated as an abrupt quantum mechanical transition. Improved formulations of the barrier-lowering mechanisms and carrier tunneling effects are derived where the dipole barrier lowering is modeled as a single exponential decay of the total surface charge density. Quantum calculations follow a two-band model in which the imaginary component of the electron wave vector in the semiconductor energy gap is obtained by including the effect of both conduction and valence states. The energy band profile effects are included in the calculation of tunneling current, and it is shown that the finite negative charge residing at the metal-semiconductor interface considerably modulates the tunneling transmission probability of carriers. Experimental results obtained from atomically clean Al-n/sup +/GaAs-nGaAs interfaces fabricated by in situ molecular-beam epitaxy (MBE) are shown to be in excellent agreement with the transport calculations. >

Modeling and characterization of an 80 V silicon LDMOSFET for emerging RFIC applications

This paper describes the design and optimization of an 80 V silicon RF LDMOSFET used in a power amplifier for base station applications. The transistor was prototyped using the doping profiles extracted from an experimental device and extensive two-dimensional (2-D) simulations were performed to characterize the DC and RF performance of the device. A good match between the measured and simulated data is reported. A simple circuit model was developed which accurately predicts the DC and RF characteristics in circuit simulators. It is shown through 2-D simulations that the LDD region in the LDMOSFET can be modeled as a JFET. A methodology for the accurate extraction of model parameters for the circuit model is discussed. It is shown that the DC and RF performances of the circuit model closely match the measured data. Advanced mixed device and circuit simulations were used to obtain S-parameters of the device which provide new insights into device physics and also the basis for statistical process control studies.

Dynamics of power MOSFET switching under unclamped inductive loading conditions

The parasitic bipolar transistor inherent in a vertical power DMOSFET structure can have a significant impact on its reliability. Unclamped Inductive Switching (UIS) tests were used to examine the reliability of DMOSFETs in extremely harsh switching conditions. The reliability of a power DMOSFET under UIS conditions is directly related to the amount of avalanche energy the device can survive. A number of DMOSFET structures were critically examined under UIS conditions to determine the impact of bipolar transistor parameters on device reliability. The UIS dynamics were studied based on the results obtained from an advanced mixed device and circuit simulator in which the internal carrier dynamics were evaluated under boundary conditions imposed by the circuit operation. It is shown that premature open base bipolar transistor breakdown can occur when the p-base sheet resistance is high. A device structure with a shallow self-aligned p/sup +/ region is shown to prevent the parasitic bipolar turn-on and avoid premature UIS breakdown without compromising the power-switching efficiency. The simulation results are shown to be in excellent agreement with the measured data under a wide range of inductive loading conditions.

Monolithically integrated power MOSFET and Schottky diode with improved reverse recovery characteristics

A power DMOSFET structure with a monolithically integrated Schottky diode located under the source contact pad is described. In this structure the source contact metallization step is also used to fabricate an epitaxial drift region Schottky diode in parallel with the parasitic body p-n junction diode of the power MOSFET. Such a structure results in significantly improved internal diode switching characteristics with no degradation in the on-state resistance and drain-source breakdown voltage. The integral power MOSFET technology was used to fabricate 30- and 45-V vertical power DMOSFETs with a reduction in peak reverse current and stored charge of more than 25% as compared to a conventional power DMOSFET. The Schottky diode consumed less than 15% of the active transistor area. >

Scaling constraints imposed by self-heating in submicron SOI MOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction. >

Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversion

The systematic optimization of low-voltage silicon power MOSFET technology is described. It is shown that device scaling using advanced fabrication technologies can result in nearly optimal performance from low-voltage silicon power MOSFETs. The details discussed include: (1) system impact; (2) unit cell optimization; (3) device and process modeling; (4) fabrication technology development; and (5) performance results. The device technologies optimized include 30-, 50-, and 100-V vertical power DMOSFETs with optimally scaled gate polysilicon and source/drain contacts. Devices with the lowest specific on-resistance, the lowest specific input capacitance, and improved high-frequency switching performance have been fabricated with excellent wafer yield. This is the first successful demonstration of device scaling and its impact on performance of high-voltage and smart-power technologies. >

Failure mechanisms of IGBTs under short-circuit and clamped inductive switching stress

The application of insulated gate bipolar transistors (IGBTs) in high-power converters subjects them to high-transient electrical stress such as short-circuit switching and turn-off under clamped inductive load (CIL). Robustness of IGBTs under high-stress conditions is an important requirement. Due to package limitations and thermal parameters of the semiconductor, significant self-heating occurs under conditions of high-power dissipation, eventually leading to thermal breakdown of the device. The presence of a parasitic thyristor also affects the robustness of the device. In order to develop optimized IGBTs that can withstand high-circuit stress, it is important to first understand the mechanism of device failure under various stress conditions. In this paper, failure mechanisms during short-circuit and clamped inductive switching stress are investigated for latchup-free as well as latchup-prone punchthrough IGBTs. It is shown that short-circuit and clamped inductive switching cannot be considered equivalent in the evaluation of a device safe operating area (SOA). The location of thermal failure of latchup-free punchthrough IGBTs is shown to be different for the two switching stresses.

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V/sub DB/=55 V (R/sub sp/=0.2 m Omega -cm/sup 2/, k/sub D/=5.7 Omega -pF) and V/sub DB/=35 V (R/sub sp/=0.15 m Omega -cm/sup 2/, k/sub D/=4.3 Omega -PF) were developed where V/sub DB/ is the drain-source avalanche breakdown voltage, R/sub sp/ is the specific on-state resistance, and k/sub D/=R/sub sp/C/sub sp/ is the input device technology factor where C/sub sp/ is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model. >