Charles Steven Korman

A 50-V, 0.7-m Omega *cm/sup 2/, vertical-power DMOSFET

A 50-V vertical power MOSFET with extremely low specific on resistance is reported. Devices with a cell density as high as 8 million cells/in/sup 2/ and capable of switching 160 A of current have been successfully fabricated using an improved fabrication technology which used low processing temperatures, double-layer interlevel dielectric, shallow source implants, and an improved source contact metallurgy. The lowest measured specific on resistances are 0.8 and 0.7 m Omega *cm/sup 2/, respectively, under continuous and pulsed bias conditions for FETs capable of blocking 50 V in the reverse direction. This result represents the best ever reported forward conductivity for a 50-V power MOSFET.<<ETX>>

High-performance vertical-power DMOSFETs with selectively silicided gate and source regions

A power FET (field-effect transistor) structure with selectively silicided gate and source region is described. This structure simultaneously lowers the gate sheet-resistance and the source contact resistance. The gate-source isolation was provided by plasma etching conformally deposited chemical vapor deposition (CVD) oxide using a photoresist mask. This structure has resulted in an order of magnitude improvement in the gate sheet resistance and about 25% improvements in the devices on-resistance (the resistance when conducting in the on-state) compared to previously reported nonsilicided conventional power FETs. Extremely low-resistance Al-TiW-TiSi/sub 2/ metallurgy with in situ sputter etching of the silicide surface prior to TiW deposition contributed to the reduction in the on-state resistance. Vertical-power DMOSFETs (double-diffused MOSFET) fabricated using this technology have a specific on-resistance of 0.53 Omega cm/sup 2/ for devices capable of blocking 50 V in the off state.<<ETX>>

Embedded magnetics for integrated power

A new transformer/inductor technology is introduced which is suitable for integrated power for multichip modules (MCM), involving both digital and microwave chips. The transformer/inductor is embedded within the ceramic substrate, as are the chips and other components. It provides for extremely tight secondary side circuit layouts, with very low and fixed leakage inductance. The core consists of a bottom ferrite plate and the winding is constructed using high density interconnect techniques (HDI) such as laminating dielectric layers and depositing winding metals using sputtering followed by electroplating. Winding patterns are etched using photoresist and wet etching techniques. And multiple vias are used to connect different primary and secondary winding layers A conformal metal mask is used to laser-drill through (large) holes for the posts of the top part of the core. An experimental 50-Watt, 6-pole transformer has been built using these techniques. It operates at 1.0 MHz with efficiency approaching 98.5% and has net height of about 0.08 inch.

Ultralow resistance, selectively silicided VDMOS FETs for high-frequency power switching applications fabricated using sidewall oxide spacer technology

The authors report on the design, fabrication, and performance of a high-cell-density, high-frequency, reliable power FET structure fabricated using self-aligned silicide technology. A high-temperature stable TiSi/sub 2/-based power FET process was developed and applied to fabricate scaled 50-V VDMOS FETs. Power FETs with a variety of cell designs to minimize the on-resistance and capacitance, to increase the packing density and to improve device ruggedness were fabricated and tested under DC and transient switching conditions with resistive and inductive loads. For the first time, silicided space power FETs with a specific on-resistance (R/sub sp/) of 0.5 m Omega -cm/sup 2/ and capable of blocking 50 V in the off-state have been demonstrated. Devices with die sizes of 25 mil*25 mil (I/sub DS/=4 A) and 200 mil*230 mil (I/sub DS/>160 A) and cell density as high as 8*10/sup 6/ cells/in have been successfully fabricated with excellent gate yield. These devices have 10* small gate sheet resistance, 5* smaller capacitance, and 3* smaller R/sub sp/ compared to previously best reported power FETs. Significant improvement in the wafer yield was demonstrated for silicided FETs processed based on rapidly thermally annealed silicide. These devices have significantly improved ruggedness characteristics. >

Mechanical design methodology for lightweight deployable solar electric system for commercial rooftops

A lightweight deployable solar electric system has been designed for commercial rooftops. In this novel concept the modules are mechanically attached in a hinged folding string and are not attached to a normal ballasted support system. This system can be mounted on a commercial rooftop with much lower cost and weight than a traditional ballasted system. This configuration provides a number of unique structural challenges that are addressed by a combination of structural analysis and testing. This paper discusses the methodology used to design and evaluate the system under wind and snow loading. As part of the design process, finite element modeling, structural component testing, and wind tunnel testing were utilized.

DOE Solar Energy Technologies Program TPP Final Report - A Value Chain Partnership to Accelerate U.S. PV Industry Growth, GE Global Research

General Electric’s (GE) DOE Solar Energy Technologies TPP program encompassesd development in critical areas of the photovoltaic value chain that affected the LCOE for systems in the U.S. This was a complete view across the value chain, from materials to rooftops, to identify opportunities for cost reductions in order to realize the Department of Energy’s cost targets for 2010 and 2015. GE identified a number of strategic partners with proven leadership in their respective technology areas to accelerate along the path to commercialization. GE targeted both residential and commercial rooftop scale systems. To achieve these goals, General Electric and its partners investigated three photovoltaic pathways that included bifacial high-efficiency silicon cells and modules, low-cost multicrystalline silicon cells and modules and flexible thin film modules. In addition to these technologies, the balance of system for residential and commercial installations were also investigated. Innovative system installation strategies were pursed as an additional avenue for cost reduction.