P. A. Piacente

A 50-V, 0.7-m Omega *cm/sup 2/, vertical-power DMOSFET

A 50-V vertical power MOSFET with extremely low specific on resistance is reported. Devices with a cell density as high as 8 million cells/in/sup 2/ and capable of switching 160 A of current have been successfully fabricated using an improved fabrication technology which used low processing temperatures, double-layer interlevel dielectric, shallow source implants, and an improved source contact metallurgy. The lowest measured specific on resistances are 0.8 and 0.7 m Omega *cm/sup 2/, respectively, under continuous and pulsed bias conditions for FETs capable of blocking 50 V in the reverse direction. This result represents the best ever reported forward conductivity for a 50-V power MOSFET.<<ETX>>

High-performance vertical-power DMOSFETs with selectively silicided gate and source regions

A power FET (field-effect transistor) structure with selectively silicided gate and source region is described. This structure simultaneously lowers the gate sheet-resistance and the source contact resistance. The gate-source isolation was provided by plasma etching conformally deposited chemical vapor deposition (CVD) oxide using a photoresist mask. This structure has resulted in an order of magnitude improvement in the gate sheet resistance and about 25% improvements in the devices on-resistance (the resistance when conducting in the on-state) compared to previously reported nonsilicided conventional power FETs. Extremely low-resistance Al-TiW-TiSi/sub 2/ metallurgy with in situ sputter etching of the silicide surface prior to TiW deposition contributed to the reduction in the on-state resistance. Vertical-power DMOSFETs (double-diffused MOSFET) fabricated using this technology have a specific on-resistance of 0.53 Omega cm/sup 2/ for devices capable of blocking 50 V in the off state.<<ETX>>

Blanket LVD tungsten silicide technology for smart power applications

A high-frequency power MOSFET structure fabricated using blanket deposited LPCVD (low-pressure chemical vapor deposition) WSi/sub 2/ gate and selectively deposited LPCVD tungsten source contact metallurgy is reported. A high-density power MOSFET technology suitable for smart power applications which simultaneously lowers the gate sheet resistance and source contact resistance is discussed. This technology was used to fabricate 30-V and 50-V power FETs with excellent high-frequency performances. The measured specific on-resistance R/sub sp/, specific input capacitance C/sub sp/, and switching times are among the lowest reported in the literature for any power FET structure in this reverse blocking voltage range.<<ETX>>

Formation and properties of rapid thermally annealed TiSi2 on lightly doped and heavily implanted silicon

Detailed material and electrical characteristics of rapid thermally annealed (RTA) TiSi2 on doped silicon are presented using transmission electron microscopy, Rutherford backscattering spectrometry, secondary ion mass spectrometry (SIMS), Auger analysis, and four‐point probe measurements. TiSi2 films with varying sheet resistances were formed on lightly doped and heavily arsenic and phosphorus implanted 〈100〉 silicon by rf sputtering titanium and forming the silicide using two‐step flash anneals at different temperatures. It is shown that the silicide sheet resistance is a sensitive function of the silicon surface condition prior to titanium sputtering; in particular, silicide films formed on heavily implanted silicon had significantly higher sheet resistance compared to films formed under identical conditions on lightly doped prime silicon. The higher silicide sheet resistance resulted because of the surface damage created during arsenic and phosphorus implantation and higher silicon dopant concentratio...

Selectively silicided vertical power double‐diffused metal–oxide semiconductor field effect transistors for high‐frequency power switching applications

A new power field effect transistor (FET) structure with selectively silicided gate and source regions is described. This structure simultaneously lowers the gate sheet resistance and source contact resistance. Vertical power double‐diffused metal‐oxide semiconductor field effect transistors fabricated using this technology have a specific on‐resistance of 0.53 mΩ cm2 for devices capable of blocking 50 V in the off‐state. Devices with cell density as high as 4 million cells/in.2 and die size as large as 200×220 mil have been successfully fabricated with excellent gate yield. These results represent the best ever reported forward conductivities for any type of power FET in the 50‐V reverse blocking range. Comparison of selectively silicided power FET’s with state of the art commercial nonsilicided FET’s indicates that the former have an order‐of‐magnitude lower gate sheet resistance, 8× smaller on‐resistance, and 2× smaller input capacitance.

Selective CVD tungsten via plugs for multilevel metallization

Use of selective-metal CVD tungsten is shown to be a viable method of filling small via holes in multilevel metal integrated circuits. The method specifically described utilizes Mo/TiW as the first-level interconnection/contacting metallization (M1), a planarized interlevel dielectric, straight via holes filled with tungsten, and AL second-level metal (M2). This methodology solves the problems of variable via depth encountered in integrated circuits especially when interlevel dielectrics are planarized and whenever design rules are utilized which allow for stacked and unstacked via connections to underlying features at widely varying topological height. The method also provides a means of greatly reducing metal interconnection pitch.

Ultralow resistance, selectively silicided VDMOS FETs for high-frequency power switching applications fabricated using sidewall oxide spacer technology

The authors report on the design, fabrication, and performance of a high-cell-density, high-frequency, reliable power FET structure fabricated using self-aligned silicide technology. A high-temperature stable TiSi/sub 2/-based power FET process was developed and applied to fabricate scaled 50-V VDMOS FETs. Power FETs with a variety of cell designs to minimize the on-resistance and capacitance, to increase the packing density and to improve device ruggedness were fabricated and tested under DC and transient switching conditions with resistive and inductive loads. For the first time, silicided space power FETs with a specific on-resistance (R/sub sp/) of 0.5 m Omega -cm/sup 2/ and capable of blocking 50 V in the off-state have been demonstrated. Devices with die sizes of 25 mil*25 mil (I/sub DS/=4 A) and 200 mil*230 mil (I/sub DS/>160 A) and cell density as high as 8*10/sup 6/ cells/in have been successfully fabricated with excellent gate yield. These devices have 10* small gate sheet resistance, 5* smaller capacitance, and 3* smaller R/sub sp/ compared to previously best reported power FETs. Significant improvement in the wafer yield was demonstrated for silicided FETs processed based on rapidly thermally annealed silicide. These devices have significantly improved ruggedness characteristics. >

Thermal stability of platinum silicide contacts to silicon with molybdenum as final metallization

We have studied molybdenum as a final metallization level over platinum silicide contacts for very large scale integration (VLSI) application. Molybdenum has been chosen owing to its good metallurgical and electrical properties. The Mo/PtSi contacts to n+ and p+ silicon have been found to be stable to heat treatments up to 700 °C for several hours. Values of the specific contact resistance range from ∼5 Ω μm2 for a 60‐min heat treatment at 400 °C to ∼40–80 Ω μm2 for a 120‐min treatment at 700 °C.