N.P. Pham

Through-wafer copper electroplating for three-dimensional interconnects

Through-wafer electrical connections are becoming increasingly important for three-dimensional integrated circuits, microelectromechanical systems packaging and radio-frequency components. In this paper, we report our current results on the formation of through-wafer metal plugs using the copper electroplating technique. Several approaches for via filling are investigated, such as filling before or after wafer thinning. Among the methods experimented, the one-side Cu plating and bottom-up filling appears to be the most suitable technique for copper filling into high aspect ratio vias. Using this method, we demonstrate the successful filling of vias with an aspect ratio of up to 7. Copper plugs as small as 20 × 20 μm2 are obtained uniformly over 4 inch Si wafers.

Spray coating of photoresist for pattern transfer on high topography surfaces

In this paper, a new method of photoresist coating, direct spray coating, is studied. This method is especially suited to coat high topography surfaces for some special applications in microelectromechanical systems, radio frequency components and packaging. The most suitable photoresist type and coating process are found. The influence of several coating parameters on the thickness and uniformity of the photoresist layer is investigated. A model describing the dependence of the thickness on the major parameters is presented. Very promising results are obtained using spray coating for the fabrication of several three-dimensional structures.

Photoresist coating methods for the integration of novel 3-D RF microstructures

This paper presents three coating methods of photoresist on large three-dimensional (3-D) topography surfaces. Two special methods, spray and electrodeposition (ED) are introduced and investigated for the fabrication of 3-D microstructures and RF-MEMS devices. Characteristics of each method as well as its advantage and disadvantages are outlined. A comparison is made to point out the most suitable coating method in terms of complexity, performance and type of application. The potential of these coating methods is demonstrated through several applications such as fabrication of multilevel micromachined structures and RF MEMS devices.

IC-compatible two-level bulk micromachining process module for RF silicon technology

This paper presents a novel two-level silicon bulk micromachining for integration of RF devices. The RF devices are fabricated at the frontside of Si(100) wafers using conventional IC technology. A post-processing module is applied from the wafer backside with precise alignment to the frontside. This module can provide a blanket ground plane at an optimum position beneath the wafer surface, a frontside contact from the wafer surface to that ground plane, and trenches to suppress crosstalk through the conductive silicon by adding two mask levels. An extension to four masks allows for an integration of large passive components beneath circuitry for a much reduced chip area, lowering chip size and cost. The feasibility of the novel post-process module is demonstrated through the fabrication of microstrip transmission lines, conductor-backed spiral inductors, trench-barriers against crosstalk through the conductive silicon substrate, and high-quality subsurface spiral inductors.

A micromachining post-process module for RF silicon technology

A bulk-micromachining post-process module, based on two-level structuring of RF silicon substrates and a 4-/spl mu/m thick one-level sub-surface metal pattern, is presented. This allows for fabricating three-dimensional structures for novel RF components and has potential in more compact integration. Next to a concise description of the relevant aspects of the fabrication process, mechanical stability of the postprocessed wafers is analyzed. Sub-surface spiral inductors with good quality and low coupling to inductors built at the wafer surface are presented, thus demonstrating the feasibility of three-dimensional integration of RF components.

Substrate options and add-on process modules for monolithic RF silicon technology

Add-on process modules as enhancements of standard high-frequency silicon integration processes are discussed. Such modules can be added without any interference with the core process before (pre-process modules), during (mid-process modules), or after (post-process modules) the circuit integration. High-resistivity silicon substrates, the patterned metal ground shield, and bulk micromachining are presented as examples in each category, respectively.

IC-compatible process for pattern transfer in deep wells for integration of RF components

An IC-compatible process for pattern transfer in deep wells and cavities for the integration of RF components is presented. After an anisotropic wet etching step used to define the optimum position of the ground plane, structures need to be patterned on the bottom of 250-400 micrometers dep etched grooves, trenches or cavities to realize wafer- through contact holes and metal patterns. Thick positive photoresist such as AZ4562 and ma-P275 are used. Modified resist spinning procedure and soft bake process resulted in a good coverage of the etched cavities, even for the deeper ones. The effect of resist thickness and spinning procedure on coating defect density and resolution loss is investigated and optimum conditions are found. A few examples of structures realized using the process described here are shown to indicate the potential and restrictions of this process.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Characterization of a bulk-micromachined post-process module: for silicon RF technology

In spite of the many advantages of state-of-the-art silicon technology, the lack of a RF ground plane at sufficient distance beneath the surface and the frontside contact to it are likely to present considerable shortcomings for future radiofrequency (RF) applications. Further, the RF crosstalk through the conductive silicon substrate cannot easily be minimized. By the local removal of the substrate-silicon, the crosstalk and loss can largely be reduced. In order to overcome these shortcomings, a novel post-processing technology, applicable to any industrial integration process, is proposed and characterized in this paper.

IC-Compatible Two-level Bulk Micromachining for RF Silicon Technology

This paper presents a novel two-level silicon bulk micromachining for integration of RF (radio frequency) devices. The RF devices are fabricated at the frontside of Si (100) wafers using conventional IC technology. A post-processing module is applied from the wafer backside. This module provides a blanket ground plane at an optimum position beneath the wafer surface, a front-side contact from the wafer surface to that ground plane and trenches to suppress cross talk through the conductive silicon. Moreover, due to the front-side RF ground contact, compatibility to conventional packaging is maintained. The feasibility of the new postprocess module is demonstrated through the fabrication of microstrip transmission lines and conductor-backed spiral inductors.

Through-Wafer Copper Electroplating for RF Silicon Technology

Silicon micromachining techniques are powerful tools to realize three-dimensional (3D) structures thus allowing a more compact-integration of RF components in silicon. In this paper a new approach consisting of deep vertical through-wafer vias and copper metallization for RF silicon integration is introduced. A novel technique to fill the dry etched, high-aspect ratio, closely spaced vias is presented. Vias as small as 5 μm in diameter and with an aspect ratio of more than 10 are filled completely by copper electroplating without any void or defect. The fabrication process and the electrical characterization of the through-wafer Cu plugs are presented. Several novel RF structures with throughwafer connections are realized successfully using the technique developed.