Kab-jin Nam

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC and AC performances of Si NW MOSFETs on NW diameter (DNW) and gate oxide thickness has been investigated. A Si NW device with the scaled DNW of 9 nm and thin equivalent oxide thickness (EOT) of 0.9 nm improved both on-current and electrostatic characteristics. Finally, a Nanowire-On-Insulator (NOI) structure has been proposed to enhance the AC performance of a multiple-stacked NWs structure, which improves DC performance but has the issue of high parasitic capacitance. As a result, the simulated AC performance of a triple-NOI structure was improved by around 20% compared to conventional triple NW structure.

Hot carrier reliability characterization in consideration of self-heating in FinFET technology

A severity of hot carrier injection (HCI) in PFET becomes worse than NFET at elevated temperatures. This new observation is further found to be due to the coupled self-heating effects (SHE) during DC HCI stress (also a higher Ea in PFET HCI), rather than the negative bias temperature instability (NBTI) effect during HCI stress. Furthermore, in order to guarantee the precise estimation of HCI under circuit level AC condition, a new empirical HCI lifetime model decoupled from the SHE is proposed, which is further verified by the Si data from nanosecond pulsed waveform HCI stress and Ring Oscillator stress results.

A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

Improvement of Performance and Data Retention Characteristics of Sub-50nm DRAM by HfSiON Gate Dielectric

For the first time, we have successfully integrated HfSiON gate dielectric to DRAM and obtained excellent data retention time. Lower gate leakage current and better mobility of HfSiON than plasma nitrided oxide resulted in a 22% smaller propagation delay measured at CMOS inverter as well as one order of magnitude lower stand-by current for DRAM. Optimized gate poly-Si reoxidation and high Vt of HfSiON cell Tr increased DRAM data retention time as much as 2 times longer than plasma nitrided oxide. We demonstrated that HfSiON could enhance performance and be beneficial to date retention time of high thermal budget DRAM at the same time.

Investigation of hot carrier effects in n-MOSFETs thick oxide with HfSiON and SiON gate dielectrics

This paper reports the reliability characteristics of poly gated n-MOSFETs with HfSiON and SiON gate dielectrics in both thin and thick oxide of dual gate oxide scheme. Hot carrier stress (HCS) at Isub, max condition on thick oxide is found to be the most critical part among the various reliability concerns. Regardless of gate dielectric and gate oxide thickness, the degradation behavior of the condition of Isub, max and Vg=Vd HCS is mainly SS increase and Vth shift, respectively. Therefore, for precise evaluation of the device reliability, it is necessary that HC immunity at Isub, max stress should be checked in thick oxide transistor below 50 nm design rule era.

Hole trap effect on time-dependent-dielectric breakdown (TDDB) of high-voltage peripheral nMOSFETs in flash memory application

In this work, the TDDB mechanism in high-voltage nMOSFETs with high-density of pre-existing defects in the gate oxide is investigated. In contrast to the traditional nMOSFETs with very few defects in the gate oxide, the additional hole trapping through the stress-induced generated defects close to the gate side not only induce longer fail time, but also induce smaller voltage acceleration factor and lower 10-year Vmax.

Investigation of hot carrier degradation in bulk FinFET

In this paper, a physical mechanism for hot carrier injection (HCI) induced trap generation and degradation in bulk FinFETs is investigated and verified with both experiment and simulation evidence. HCI degradation is mainly caused by interface states generated by drain avalanche hot carrier injection. From this model, impact ionization intensity, location and trapping immunity are proposed as key parameters to modulate HCI degradation. HCI reliability in I/O FinFETs is severely degraded with respect to planar FETs because of the enhanced capability of the gate to control the channel potential profiles increasing the intensity of the lateral E-field in comparison with planar devices. Based on this FinFET HCI mechanism, we have successfully optimized source/drain junction process to achieve reliable HCI characteristics for 14nm and 10nm FinFET devices.

Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB

In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (Ev) lowers the Eox and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.

Gate oxide effect on wafer level reliability of next generation dram transistors

Wafer level reliability (WLR) issues of DRAM cell and peripheral transistors are discussed. Since the 70 nm technology node, recessed transistors have been accepted for assuring data retention time of DRAM cell transistors. Various recessed transistor structures suggest that the most important issue in reliability, in addition to optimizing data retention time, is the elimination of local regions of concentrated electric fields. In this paper, by modulating the cell gate oxidation process, local field concentration is effectively reduced. Particularly, the introduction of a radical oxidation process can create cell transistors that are more immune to Fowler-Nordheim (F-N) stress, which can degrade interface quality during cell transistor operation. On the other had, for DRAM peripheral transistors, for DRAM peripheral transistors, which currently use dual poly-Si gates and SiON dielectrics, high-k/metal gate (HK/MG) structure are expected to be adopted at the 20 nm technology node for improved equivalent oxide thickness (EOT) scaling. The high thermal budget of a conventional DRAM manufacturing process can significantly impact HK/MG WLR issues. However, we have evaluated reliability characteristics for HK/MG WLR on DRAM cell and peripheral devices, and concluded that WLR issues will not be critical for operation.