Young-wook Park

A process technology for 1 giga-bit DRAM

In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSi/sub x/ gate, Self-Aligned Contact (SAG), and simple stack capacitor cell using (Ba,Sr)TiO/sub 3/ (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.

Conformal CVD-ruthenium process for MIM capacitor in giga-bit DRAMs

To realize the gigabit-scale DRAM capacitor, it is necessary to develop new electrode materials instead of poly-Si and TiN. Among them, Ruthenium has been the most promising electrode material in advance of Pt or Ir because it can be easily etched by oxygen plasma and shows good electrical properties as a capacitor electrode. But, a CVD-Ru film with good conformality and smooth morphology actually applicable to gigabit-scale DRAM generations has not been known up to now. In this work, we present the development of novel CVD process for application in real device with 3-dimensional structure and the electrical properties of capacitor using CVD-Ru electrode.

Electrical Properties of Crystalline Ta2O5 with Ru Electrode

As one candidate capacitor for dynamic random access memories (DRAMs) of 4 Gbit and beyond, we investigated the electrical properties of Ru/Ta2O5/Ru. In this paper, the dielectric constant of Ta2O5 was measured as a function of annealing temperature and, also, its dependence on film thickness was studied. The effect of postannealing, which was performed after forming a capacitor, on the leakage current of Ru/crystalline-Ta2O5/Ru capacitor was evaluated. Additionally, the leakage current was investigated as a function of Ta2O5 film thickness. Through these experiments, a reliable 7 A Toxeq. of Ta2O5 with a Ru electrode was obtained, which indicates that the Ru/crystalline-Ta2O5/Ru capacitor is a promising candidate for DRAMs of 4 Gbit and beyond.

Effects of annealing of (Ba,Sr)RuO3 bottom electrodes on the electrical properties of (Ba,Sr)TiO3 thin films

The annealing of (Ba,Sr)RuO3 films which are structurally and chemically matched with (Ba,Sr)TiO3 films was performed in oxygen and nitrogen atmospheres in the temperature range of 600–750 °C for 30 min. The effects of annealing the (Ba,Sr)RuO3 on the physical and electrical properties of the (Ba,Sr)TiO3 films were investigated. The x-ray diffraction peak of the annealed (Ba,Sr)RuO3 film at high temperatures revealed that the (Ba,Sr)TiO3 film is thermally more stable than RuO2. The (Ba,Sr)RuO3 film under N2 annealed showed lower electrical resistivity and larger surface roughness compared with those under O2. In addition, from the sequential two-step annealing process using O2 and N2, and by reversing the annealing sequence, the electrical resistivity and the surface roughness of the (Ba,Sr)RuO3 film turned out to be reversible. The (Ba,Sr)TiO3 film on the N2 annealed (Ba,Sr)RuO3 showed a higher leakage current than that on the O2 annealed bottom electrode because rough surface can cause a high local elec...

Performance elements for 28nm gate length bulk devices with gate first high-k metal gate

In this paper, we describe the performance elements used in our 28nm bulk devices with the gate first high-k/metal gate scheme for high performance applications. By using the innovative stressor integrations including improved stress memory technique (SMT), optimized embedded SiGe process and dual stress liner, Ieff of ∼540/360 uA/um have been obtained for NMOS and PMOS respectively with the gate length of 28nm and pitch of 113.4nm (Ioff =100 nA/um, Vdd=0.85V). Good Vth mis-match (Avt of ∼2.4 mV-um) has been achieved for SRAM devices with the high-k/metal gate, signal-noise-ratio of ∼0.2V has been demonstrated in the high performance SRAM cell (0.152 um2) with Vdd of 0.85V.

Ductility Characteristics of Partially Restrained Beam-To-Column Composite Connections in Concrete Filled Square Tubes

This paper presents the development of an improved detail in partially restrained beam-to-column composite connections in concrete filled square tubes and the evaluation of its structural characteristics and behaviour under monotonic and cyclic loading. Studies for the bolted seat-angle connections of existing partially restrained composite connection (PR-CC) details have been conducted mostly on shallow beam-to-column connections. In case of deep beam-to-column connections, the fabrication becomes complicated because the sizes of the seat-angles are larger than the connections, and the number of bolts and welding length are increased. This study suggests a new detail of PR-CC which can be applied to concrete-filled tubular structures incorporating the effect of composite slabs and the performance for construction work. A welded bottom beam flange connection is proposed to enhance the capacity of the bottom of the connection and to improve ductility and fabrication. In addition, a reduced beam section (RBS) is adapted for the bottom beam flange to examine its effect on ductility. A seat-angle connection with penetrating bolts is also suggested and compared with the welded bottom beam flange connection. Both monotonic and cyclic loading tests are conducted on the five full scale specimens to compare and evaluate their ductility characteristics.

Superior ArF PR etching selectivity and via CD control using fluorocarbon polymer deposition technique for 45nm-node

The fabrication process of semiconductor is more and more difficult as dimension scaling down. Especially, the via critical dimension (CD) and profile controls are the main challenges of ArF photo resist (PR) masking steps. This paper presents the unique technique using the masking protection step which is added at appropriate step in the via etch process to improve the via post etch profile. This technique has many merits such as using of single PR, easy control of CD, simple etching process and lower cost. The tri-layer process is currently is used in via process in device of 45nm-node. It is expected the much complicated photo layers are needed for device beyond 45nm-node. In this paper, a novel technique by controlling deposition of polymer from the protection layer is proposed. The results show superior PR etching selectivity to achieve good via CD and post etch profile and good clean efficiency of deposited polymer around via bottom and side wall.

DRAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug

As DRAM downscaling approaches the 0.1 /spl mu/m generation, problems related to transistor short channel effects, storage capacitance, gap filling of high aspect ratio patterns, and leakage currents through each module must be solved. Among these, processing around the storage node self-aligned contact (SAC) is the most critical problem for integration of capacitor-on-bitline (COB) DRAM devices because it is one of the deepest contacts with high aspect ratio; and it reaches the cell transistor junction. However, few reports have addressed this issue, while others have been reported elsewhere (Song et al., 2000; Jeong et al., 2000; Won et al., 2000; Kim et al., 2000). In this paper, a novel process of bitline spacerless storage node SAC and Ru-Ta/sub 2/O/sub 5/-Ru (RIR) capacitor with TiN contact plug is studied for the integration of 0.1 /spl mu/m design-rule based DRAMs. It was found that the spacerless SAC process made downscaling to the 0.1 /spl mu/m design-rule possible and also that it has better electrical properties than the conventional SAC.

Development of Ru/Ta/sub 2/O/sub 5//Ru capacitor technology for giga-scale DRAMs

In this paper, the Ru/crystalline-Ta/sub 2/O/sub 5//Ru capacitor was investigated. We studied the electrical properties and introduced an Al/sub 2/O/sub 3/ capping layer to prohibit the degradation of the leakage current resulted from H/sub 2/ annealing. Also, the Ru cylinder-type structure was suggested as a 3-dimensional storage node shape and was confirmed in its extendibility to 0.1 /spl mu/m-scaled design rule.