Kai Blekker

Controllable p-type doping of GaAs nanowires during vapor-liquid-solid growth

We report on controlled p-type doping of GaAs nanowires grown by metal-organic vapor-phase epitaxy on (111)B GaAs substrates using the vapor-liquid-solid growth mode. p-type doping of GaAs nanowires was realized by an additional diethyl zinc flow during the growth. Compared to nominally undoped structures, the current increases by more than six orders of magnitude. The transfer characteristics of fabricated nanowire metal-insulator-semiconductor field-effect transistor devices proved p-type conductivity. By adjusting the II/III ratio, controlled doping concentrations from 4.6×1018 up to 2.3×1019 cm−3 could be achieved at a growth temperature of 400 °C. The doping concentrations were estimated from electrical conductivity measurements applied to single nanowires with different diameters. This estimation is based on a mobility versus carrier concentration model with surface depletion included.

High Transconductance MISFET With a Single InAs Nanowire Channel

Metal-insulator field-effect transistors (FETs) are fabricated using a single n-InAs nanowire (NW) with a diameter of d = 50 nm as a channel and a silicon nitride gate dielectric. The gate length and dielectric scaling behavior is experimentally studied by means of dc output- and transfer-characteristics and is modeled using the long-channel MOSFET equations. The device properties are studied for an insulating layer thickness of 20-90 nm, while the gate length is varied from 1 to 5 mum. The InAs NW FETs exhibit an excellent saturation behavior and best breakdown voltage values of V BR > 3 V. The channel current divided by diameter d of an NW reaches 3 A/mm. A maximum normalized transconductance gm /d > 2 S/mm at room temperature is routinely measured for devices with a gate length of les 2 mum and a gate dielectric layer thickness of les 30 nm.

n-Type Doping of Vapor–Liquid–Solid Grown GaAs Nanowires

In this letter, n-type doping of GaAs nanowires grown by metal–organic vapor phase epitaxy in the vapor–liquid–solid growth mode on (111)B GaAs substrates is reported. A low growth temperature of 400°C is adjusted in order to exclude shell growth. The impact of doping precursors on the morphology of GaAs nanowires was investigated. Tetraethyl tin as doping precursor enables heavily n-type doped GaAs nanowires in a relatively small process window while no doping effect could be found for ditertiarybutylsilane. Electrical measurements carried out on single nanowires reveal an axially non-uniform doping profile. Within a number of wires from the same run, the donor concentrations ND of GaAs nanowires are found to vary from 7 × 1017 cm-3 to 2 × 1018 cm-3. The n-type conductivity is proven by the transfer characteristics of fabricated nanowire metal–insulator-semiconductor field-effect transistor devices.

High-Frequency Measurements on InAs Nanowire Field-Effect Transistors Using Coplanar Waveguide Contacts

In this paper, a 50-μm-pitch coplanar waveguide pattern for on-wafer high-frequency measurements on nanowire FET is used. The contact structure exhibits relatively large parasitic elements in comparison to the intrinsic device making a precise deembedding both necessary and challenging. A single InAs nanowire FET with a large gate length of 1.4 μm possesses after deembedding a maximum stable gain higher than 30 dB and a maximum oscillation frequency of 15 GHz. The gate length scaling of the nanowire transistor is modeled using the experimental transconductance data of a set of transistors and an analytical model. On this basis, both the device performance and the expectation of high-frequency measurements at small gate lengths are discussed.

Scalable high-current density RTDs with low series resistance

InP-based double-barrier resonant tunnelling diodes have been optimized for high speed digital circuits. We present the scalability of high current density (JP ≈ 150 kA/cm2;) resonant tunnelling diodes in the sub-micrometer electrode area range. A small signal equivalent circuit has been developed and its parameters are precisely deduced from DC and RF measurements. Based on this model the scalability has been investigated with emphasis on a low but also scalable series resistance in order to keep the peak voltage constant. A comparison of dry and wet etching methods in the device fabrication will be presented. A multiple mesa concept has been adopted to provide reliable scalability at low emitter area (AE < 1 µm2).

High frequency characterisation of single InAs nanowire field-effect transistors

We report on a first RF characterisation of single InAs nanowire channel field-effect-transistors. The nanowires with about 30 nm diameter are transferred to a carrier substrate and contacted with a coplanar waveguide pad configuration with a pitch down to 50 mum. Magnesium oxide as well as SiNx are used as gate dielectric for high performance MISFET type field-effect-transistors. Small signal scattering parameter measurements have been performed on-wafer. The nanowire FET exhibit an ultra-small intrinsic gate-source capacitance Cgs down to a few hundred ato Farad, making a careful de-embedding of the data indispensable. First measurements have shown a maximum stable gain higher than 30 dB at low frequency and a maximum oscillation frequency of 15 GHz.

Modeling the Carrier Mobility in Nanowire Channel FET

We report on the extraction of carrier type, and mobility in semiconductor nanowires by adopting experimental nanowire field-effect transistor device data to a long channel MISFET device model. Numerous field-effect transistors were fabricated using n-InAs nanowires of a diameter of 50 nm as a channel. The I-V data of devices were analyzed at low to medium drain current in order to reduce the effect of extrinsic resistances. The gate capacitance is determined by an electro-static field simulation tool. The carrier mobility remains as the only parameter to fit experimental to modeled device data. The electron mobility in n-InAs nanowires is evaluated to µ = 13,000 cm 2 /Vs while for comparison n-ZnO nanowires exhibit a mobility of 800 cm 2 /Vs.

Single n-InAs Nanowire MIS-Field-Effect Transistor: Experimental and Simulation Results

We fabricated and characterised n-InAs nanowire field effect transistors. Nanowires were grown by metal-organic vapour-phase epitaxy (MOVPE) using the vapour-liquid-solid (VLS) growth mode. Metal-insulator field-effect transistors are fabricated using single n-InAs nanowire with a diameter of d = 50 nm as a channel and a silicon nitride gate dielectric. The gate length and gate dielectric variation are experimentally studied by means of DC output-and transfer-characteristics and is modeled using the long-channel MOSFET equations. The device properties are studied for an insulating layer thickness from 20 nm to 90 nm while the gate length is varied from 1 mum to 5 mum. The InAs nanowire field-effect transistors exhibit an excellent saturation behavior and breakdown voltage values of VBR > 3 V. The channel current divided by the diameter d of a nanowire reaches 3 A/mm. A maximum normalized transconductance gm/d > 2 S/mm at room temperature is routinely measured for devices with a gate length les 2 mum and a gate dielectric layer thickness les 30 nm. Based on Iniguezs continuous charge control model for surrounding-gate MOSFET, the device is modelled and compared to experimental data. The good agreement verifies the validity of the model and provides detailed information on transport parameters available in InAs NW.

On the temporal behavior of dc and rf characteristics of InAs nanowire MISFET

Nanowire devices have drawn increasing attention as one of the most promising candidates for logic switches. Recently; III–V nanowire MISFETs have been fabricated exhibiting extremely high transconductance [1, 2]. However, there are only a very few works on their applicability in high speed monolithic integrated circuits [3–5]. In this contribution, the temporal behavior of their dc and rf characteristics has been studied as a prerequisite for the set-up of reliable device models.

An InAs nanowire spin transistor with subthreshold slope of 20mV/dec

We have fabricated a spin transistor based on InAs nanowire. The transistor operates based on Datta-Das type spin transistor mode [1][2][3]. The spin polarized electrons are injected from the ferromagnetic electrodes and synchronized spin precession is controlled by the gate voltage through spin-orbit interaction. We have clearly observed drain current oscillation versus gate voltage as expected from the Dyakonov-Pérel mechanism. By controlling the spin precession, on/off switching is expected to be achieved with the steep slope. The best of our obtained results has shown the steepest slope of 18mV/dec to 23mV/dec near the off-state ((2n+1)π-spin rotation) where vertical electric field meats the condition of persistent spin helix (PSH) motion [3]. The present result provide alternative method of steep slope device mechanism in addition to the conventional ideas such as Tunnel FETs or impact ionization FETs.