W. Prost

Threshold logic circuit design of parallel adders using resonant tunneling devices

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed.

Controllable p-type doping of GaAs nanowires during vapor-liquid-solid growth

We report on controlled p-type doping of GaAs nanowires grown by metal-organic vapor-phase epitaxy on (111)B GaAs substrates using the vapor-liquid-solid growth mode. p-type doping of GaAs nanowires was realized by an additional diethyl zinc flow during the growth. Compared to nominally undoped structures, the current increases by more than six orders of magnitude. The transfer characteristics of fabricated nanowire metal-insulator-semiconductor field-effect transistor devices proved p-type conductivity. By adjusting the II/III ratio, controlled doping concentrations from 4.6×1018 up to 2.3×1019 cm−3 could be achieved at a growth temperature of 400 °C. The doping concentrations were estimated from electrical conductivity measurements applied to single nanowires with different diameters. This estimation is based on a mobility versus carrier concentration model with surface depletion included.

High Transconductance MISFET With a Single InAs Nanowire Channel

Metal-insulator field-effect transistors (FETs) are fabricated using a single n-InAs nanowire (NW) with a diameter of d = 50 nm as a channel and a silicon nitride gate dielectric. The gate length and dielectric scaling behavior is experimentally studied by means of dc output- and transfer-characteristics and is modeled using the long-channel MOSFET equations. The device properties are studied for an insulating layer thickness of 20-90 nm, while the gate length is varied from 1 to 5 mum. The InAs NW FETs exhibit an excellent saturation behavior and best breakdown voltage values of V BR > 3 V. The channel current divided by diameter d of an NW reaches 3 A/mm. A maximum normalized transconductance gm /d > 2 S/mm at room temperature is routinely measured for devices with a gate length of les 2 mum and a gate dielectric layer thickness of les 30 nm.

Evidence of type‐II band alignment at the ordered GaInP to GaAs heterointerface

Interfacial characteristics of Ga0.51In0.49P/GaAs heterostructures grown by metal‐organic vapor‐phase epitaxy in the temperature range from 600 °C to 730 °C were studied. Photoluminescence (PL) measurements have been used for this purpose. A PL peak with an energy of about 1.425 eV (870 nm) was continuously observed in samples containing the GaInP‐to‐GaAs interface. Excitation power dependent PL measurements show that this peak belongs to an excitonic recombination. Furthermore, a strong blue‐shift of this PL‐peak energy was observed as the excitation power increased. We attribute the 870 nm peak to the radiative recombination of spatially separated electron‐hole pairs and suggest the type‐II band alignment at the ordered GaInP to GaAs heterointerface under growth conditions reported here. Further investigations using x‐ray diffraction measurements and simulations with dynamical theory show that the lower and upper interfaces are not equivalent. This explains the absence of type‐II transition in most GaAs...

Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunnelling diodes

The manufacturability of logic circuits based on quantum tunnelling devices, namely double-barrier resonant tunnelling diodes (RTD), is studied in detail. The homogeneity and reproducibility of III/V mesa technology-based devices is experimentally evaluated and interpreted using multiple I-V characteristic simulations. The experimental sensitivity of the RTD I-V parameters on well and barrier thickness is compared with multiple I-V simulations. With shrinking minimum feature size the fluctuations in the peak current can be directly attributed to an RTD area variation caused by the increasing impact of lithography and etching on lateral dimensions. These results prove that the III/V technology fulfils the requirements for a large scale integration of RTD devices. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is presented. Detailed SPICE simulations using the experimental data show that clock and supply voltage fluctuations are tolerated up to ± 0.1 V at a supply voltage of 0.7 V. Very strong local peak voltage variations of 15 per cent in opposite directions would be necessary to have a critical impact on to the circuit functionality. Smaller deviations only affect the timing without degrading the reliability of the circuit. Consequently, the design of a stable power supply and clocking scheme is more important for the overall circuit performance than the small relative deviations of the RTD peak voltage.

Direct determination of minority carrier diffusion lengths at axial GaAs nanowire p-n junctions.

Axial GaAs nanowire p-n diodes, possibly one of the core elements of future nanowire solar cells and light emitters, were grown via the Au-assisted vapor-liquid-solid mode, contacted by electron beam lithography, and investigated using electron beam induced current measurements. The minority carrier diffusion lengths and dynamics of both, electrons and holes, were determined directly at the vicinity of the p-n junction. The generated photocurrent shows an exponential decay on both sides of the junction and the extracted diffusion lengths are about 1 order of magnitude lower compared to bulk material due to surface recombination. Moreover, the observed strong diameter-dependence is well in line with the surface-to-volume ratio of semiconductor nanowires. Estimating the surface recombination velocities clearly indicates a nonabrupt p-n junction, which is in essential agreement with the model of delayed dopant incorporation in the Au-assisted vapor-liquid-solid mechanism. Surface passivation using ammonium sulfide effectively reduces the surface recombination and thus leads to higher minority carrier diffusion lengths.

High-Speed GaN/GaInN Nanowire Array Light-Emitting Diode on Silicon(111)

The high speed on-off performance of GaN-based light-emitting diodes (LEDs) grown in c-plane direction is limited by long carrier lifetimes caused by spontaneous and piezoelectric polarization. This work demonstrates that this limitation can be overcome by m-planar core-shell InGaN/GaN nanowire LEDs grown on Si(111). Time-resolved electroluminescence studies exhibit 90-10% rise- and fall-times of about 220 ps under GHz electrical excitation. The data underline the potential of these devices for optical data communication in polymer fibers and free space.

Alignment of Semiconductor Nanowires Using Ion Beams

Gallium arsenide nanowires are grown on 100 GaAs substrates, adopting the epitaxial relation and thus growing with an angle around 35 degrees off the substrate surface. These straight nanowires are irradiated with different kinds of energetic ions. Depending on the ion species and energy, downwards or upwards bending of the nanowires is observed to increase with ion fluence. In the case of upwards bending, the nanowires can be aligned towards the ion beam direction at high fluences. Defect formation (vacancies and interstitials) within the implantation cascade is identified as the key mechanism for bending. Monte Carlo simulations of the implantation are presented to substantiate the results.

n-Type Doping of Vapor–Liquid–Solid Grown GaAs Nanowires

In this letter, n-type doping of GaAs nanowires grown by metal–organic vapor phase epitaxy in the vapor–liquid–solid growth mode on (111)B GaAs substrates is reported. A low growth temperature of 400°C is adjusted in order to exclude shell growth. The impact of doping precursors on the morphology of GaAs nanowires was investigated. Tetraethyl tin as doping precursor enables heavily n-type doped GaAs nanowires in a relatively small process window while no doping effect could be found for ditertiarybutylsilane. Electrical measurements carried out on single nanowires reveal an axially non-uniform doping profile. Within a number of wires from the same run, the donor concentrations ND of GaAs nanowires are found to vary from 7 × 1017 cm-3 to 2 × 1018 cm-3. The n-type conductivity is proven by the transfer characteristics of fabricated nanowire metal–insulator-semiconductor field-effect transistor devices.

Low-voltage MOBILE logic module based on Si/SiGe interband tunnelling diodes

Si/SiGe interband tunnelling diodes have been grown by MBE on high resistivity (n/sup -/) silicon substrates. The device enables a very low voltage, high-speed logic on a silicon substrate. A novel self-aligned diode is processed using optical lithography and dopant-selective wet chemical etching. A maximum speed index for a 60 /spl mu/m/sup 2/ anode area device is evaluated to 2.2 ns/V resulting in a switching speed of 0.5 ns. A logic latch built of two series connected diodes (MOBILE principle) is demonstrated, showing very robust logic operation at a supply voltage as low as 0.3 V. The used technology may be employed for a co-integration with both SiGe heterostructure bipolar- and field-effect transistor technology and may contribute to future low-voltage high speed logic on Si substrates.