Kai Liao

Low power adiabatic logic based on FinFETs

With the aggressive scaling of device technology, the leakage power has become the main part of power consumption, which seriously reduces the energy recovery efficiency of adiabatic logic. In this paper, a novel low-power adiabatic logic based on FinFET devices has been proposed. Due to the lower leakage current, higher on-state current and design flexibility of FinFETs, the proposed adiabatic logic shows considerable power reduction, performance improvement and area saving compared with CMOS adiabatic logic. An 8-state clock chain as the test circuit has been demonstrated based on the 32-nm FinFET Predictive Technology Model. The simulation results show that adiabatic circuit based on FinFET devices achieves a power reduction of up to 84.8% and a limiting frequency of up to 55 GHz.

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

With the technology scaling down, low power dissipation has become one of the research focuses in the field of integrated circuit design. Various types of adiabatic logics have been invented for low-power applications. However, the expanding leakage current degrades the performance of conventional adiabatic logics. In this article, a novel improved complementary pass-transistor adiabatic logic (ICPAL) based on fin-type field-effect transistor (FinFET) devices with ultra-low power dissipation has been presented. The proposed ICPAL takes full advantage of different FinFET operating modes, that is, shorted-gate mode, independent-gate mode, and low-power mode, to make a tremendous reduction in power dissipation. For explication and verification, the power dissipation of different ICPAL standard cells has been investigated and compared with other types of adiabatic circuits based on FinFETs. The results show that the ICPAL circuits have ultra-low power dissipation in a wide range of clock frequencies(30–800 MHz) under the condition of similar number of transistors, and the average reduction in power dissipation is about 23.1%, 75.0%, and 50.0% relative to 2N-2N2P, improved pass-transistor adiabatic logic, and complimentary pass-transistor adiabatic logic, respectively. Furthermore, ICPAL supports a better pre-evaluation of system power dissipation in VLSI design and has an intrinsic characteristic for the resistance to some types of side channel attacks.

Key characterization factors of accurate power modeling for FinFET circuits

Due to its excellent device features, manufacture process compatibility and diversity of the circuit structures, The FinFET is considered appropriate candidate for the conventional bulk-MOSFET in sub-22nm technology nodes. However, the power estimation CAD tools for FinFET are missing at the moment, which mainly results from the absence of FinFET power analysis and FinFET power model. Three key factors for FinFET power model are: the dimension of the look-up-tables, that to find out the most significant factors that influence FinFET power and to make them as indexes for the look-up-tables; the distance between sampling points; and the interpolation method. In this paper, various factors that may contribute to the FinFET power consumption are evaluated. Of all the factors, the continuous ones are compared with sensitivity method. As to other discrete factors, methods of building them in power model are given according to the features of the each factor and the way it influences the power. Based on the simulation result, standard cell power library model for FinFET is proposed. The research work lays foundation for accurate power analysis and modeling for high-level power analysis of FinFET circuits. Besides, these key factors are also crucial for low-power FinFET circuit design.摘要创新点FinFET由于具有良好的器件特性、制程兼容性和多种电路结构, 被认为是在22nm以下制程工艺中替代传统体硅MOSFET最有效的器件。 然而, 针对FinFET的功耗分析在现阶段仍然缺失。 本文针对FinFET不同的电路结构特点, 采用PTM 32nm FinFETs模型在HSpice上进行了详尽的功耗来源与影响因素分析: 针对电路连接模式、背栅电压、输入信号歪斜、输出电容负载、电路输入状态、以前的状态、时序动作、温度等一些可能对功耗造成影响的因素进行了一一探讨。 需要特别关注的是, 与体硅MOSFET相比, 双栅FinFET器件的阈值电压增加了一个背栅电压的控制量, 本文针对这一FinFET特点进行了着重探讨。 通过量化和比较所有的功耗影响因素, 改进了已有的功耗库模型。 本文对于低功耗设计人员与CAD软件设计人员具有指导和借鉴意义。

A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs

In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage according to the system operating frequency and operating mode, which could optimize circuit power, especially leakage power. The experimental and simulation result shows that the leakage power dissipation reduced greatly when circuits operate at the lower frequency, and the energy-delay product of FinFET circuits is reduced by 30% approximately.

Design of D flip-flops with low power-delay product based on FinFET

In this paper, FinFET has been introduced to the design of high performance D flip-flops. Based on the excellent electrical properties of FinFET, the SG-mode D flip-flop modified from original PHLFF by substituting SG-mode FinFET for planar MOSFET has a tremendous reduction of 87.0% on power-delay product (PDP). Considering the unique merits of multiple operating modes of FinFET, further optimization based on SG-mode PHLFF has been proposed to achieve lower PDP and more efficient area utilization rate. The simulation results indicate that the multi-mode PHLFF reduces the PDP by 92.6% and slightly decreases the number of transistors.

High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2 m )

To achieve high performance scalar multiplication arithmetic in Elliptic Curve Cryptography (ECC) based on GF(2m), a high-speed constant-time division module with optimized architecture is proposed in this paper. Modified from the traditional extended Euclidean Great Common Divisor (GCD) division algorithm, the presented algorithm computes a single multiplicative inverse or division in constant m iterations, i.e. m clock cycles, in GF(2m), which obtains a tremendous reduction (specifically more than 50%) on computing time compared with previous works. Combined with the meticulously optimized architecture, this novel division module achieves lower area-time complexity, which makes it an excellent option for high performance ECC design.

Research on power model of multi-mode FinFET standard cell

FinFET, because of good device characteristics, manufacture process compatibility and the diversity of the circuit structure, is considered the best candidate for the conventional bulk-MOSFETs in sub-22nm technology nodes. In this paper, power model of multi-mode FinFET standard cells are discussed and the influence that back-gate voltage of FinFETs on leakage power and internal power of standard cell circuits is analyzed. The research results will lay foundation for library-based power analysis and modeling of FinFET circuits. Besides, some consideration is also crucial for low-power FinFET circuit designs.

Improving DFA attacks on AES with unknown and random faults

Differential fault analysis (DFA) aiming at the advanced encryption standard (AES) hardware implementations has become a widely research topic. Unlike theoretical model, in real attack scenarios, popular and practical fault injection methods like supply voltage variation will introduce faults with random locations, unknown values and multibyte. For analyzing this kind of faults, the previous fault model needed six pairs of correct and faulty ciphertexts to recover the secret round-key. In this paper, on the premise of accuracy, a more efficient DFA attack with unknown and random faults is proposed. We introduce the concept of theoretical candidate number in the fault analysis. Based on this concept, the correct round-key can be identified in advance, so the proposed attack method can always use the least pairs of correct and faulty ciphertexts to accomplish the DFA attacks. To further support our opinion, random fault attacks based on voltage violation were taken on an FPGA board. Experiment results showed that about 97.3% of the attacks can be completed within 3 pairs of correct and faulty ciphertexts. Moreover, on average only 2.17 pairs of correct and faulty ciphertexts were needed to find out the correct round-key, showing significant advantage of efficiency compared with previous fault models. On the other hand, less amount of computation in the analyses can be realized with a high probability with our model, which also effectively improves the time efficiency in DFA attacks with unknown and random faults.创新点在针对AES算法的随机类型故障, 传统的多字节故障模型需要分析6个故障密文才能恢复正确的四字节密钥。为了提高分析效率, 本文提出了一种针对随机类型故障的高效率差分分析算法。在保证分析准确性的前提下, 我们利用理论密钥候选值数量的概念, 设计了一种新的故障分析算法, 该算法能够根据实际的故障注入情况, 用最少的故障密文数提前恢复密钥, 并有效减小计算复杂度。针对AES算法的实际攻击结果表明, 该算法平均只需要分析2.17个故障密文即可恢复密钥, 并且97.3%的故障攻击实例都能在3组故障密文分析内完成攻击, 有效提高了分析效率。

A combined countermeasure against DPA and implementation on DES

Differential Power Analysis (DPA) reveals the secret key from the cryptographic device by side channel power leakage. Masking and Random Delay Insertion (RDI) are two effective countermeasures against DPA attack. This paper propose a novel countermeasure which associating masking with RDI, further, Multi-Masking instead of Transformed Masking is proposed in order to defend DPA attack based on hamming distance model. The combined countermeasure is implemented on Data Encryption Standard (DES). The results show that combined countermeasure defends DPA attack with 105 power traces, and increases 40% ability against DPA.

Design of Low-Power High-Performance FinFET Standard Cells

With the leakage power becoming a most important concern in deep sub-micron designs, the advent of FinFET offers promising options due to its superior electrical properties and design flexibility. To support the VLSI digital system design flow based on the standard cells in FinFET, the building method of optimized FinFET standard cells is proposed. This method is derived on the basis of jointly optimizing the back-gate voltages and the width to length ratio of the transistors in the stacked structure in each standard cell under the premise of maintaining the performance. By employing this design method, optimized standard cells are generated and form a low-power high-performance standard cell library. Simulation results of the standard cells designed with our proposed method demonstrate that the leakage power can be reduced by a factor of 47.99 at most while the worst-case delay can achieve a maximum reduction of 10.17%. Monte Carlo simulation results illustrate that the optimized cells can gain more dependability to process variations and environmental changes. The 16-bit ripple carry adder implemented with this optimized FinFET library can obtain a maximum leakage power reduction of 59.6% and a worst-case delay reduction of 21.8%.