Kai-Shin Li

Sub-60mV-swing negative-capacitance FinFET without hysteresis

In this work, we report the first Negative-Capacitance FinFET. ALD Hf042Zr058O2 is added on top of the FinFETs gate stack. The test devices have a floating internal gate that can be electrically probed. Direct measurement found the small-signal voltage amplified by 1.6X maximum at the internal gate in agreement with the improvement of the subthreshold swing (from 87 to 55mV/decade). ION increased by >25% for the IOFF. For the first time, we demonstrate that raising HfZrO2 ferroelectricity, by annealing at higher temperature, reduces and eliminates IV hysteresis and increases the voltage gain. These discoveries will guide future theoretical and experimental work.

Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies

Ferroelectric HfZrOx (FE-HZO) FETs is experimentally demonstrated with 0.98nm CET (capacitance equivalent thickness), small hysteresis window VT (threshold voltage) shift <; 0.1V, SSfor = 42mV/dec, SSrev = 28mV/dec, and switch-off <; 0.2V. The optimum ALD process leads single monolayer SiOx for IL (interfacial layer) and low gate leakage current. The FE-HZO FETs is operated at room temperature and 150K to obtain beyond the physical limitation of Boltzmann tyranny, and the extracted body factors are m = 0.67 and m = 0.89 for VDS = 0.1 and 0.5 V, respectively, to confirm the negative capacitance (NC) effect. There are two proposed strategies to reach hysteresis-free, including FE-HZO/epi-Ge/Si FETs with experimentally VT shift 3mV in hysteresis window, and 3nm-thick FE-HZO resulting hysteresis-free and sub-0.2V switching by numerical simulation.

Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing

For the first time, a four-layer HfOx-based 3D vertical RRAM, the “tallest” one ever reported, is developed and integrated with FinFET selector. Uniform memory performance across four layers is obtained (±0.8V switching, 106 endurance, 104s@125°C). SPICE simulations show that high drive current of pillar select transistors is required for high-rise 3D RRAM arrays. The four-layer 3D RRAM is a versatile computing unit for (a) brain-inspired computing and (b) in-memory computing. (a) Stochastic RRAM synapses enable robust pattern learning for a 3D neuromorphic visual system. The 3D architecture with dense and balanced neuron-synapse connections provides 55% EDP savings and 74% VDD reduction (enhanced robustness) compared with conventional 2D architecture; (b) in-memory logic such as NAND, NOR, and bit shift, are essential elements for hyper-dimensional computing. Utilizing the unique vertical connection of 3D RRAM cells, these operations are performed with little data movement.

Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication

A sidewall electrode technology was successfully developed for the first time in this study, improving the understanding of the working mechanism in an ultra small, functional HfO₂-based resistive random access memory (RRAM) device (<; 1 × 3 nm²). This technology exhibits potential for application in atomic-scale memories. The 1 × 3 nm² RRAM device exhibited an excellent performance, featuring a high endurance of more than 10⁴ cycles, a large on/off verified window (>100), and reasonable reliability (stress time > 10³ s, 2 × 10⁴ h at 250 °C). Furthermore, the 1 × 3 nm² RRAM device exhibited distinctive unipolar behavior when a high voltage and rapid switching operation (7 V, 50 ns) were applied, and a switching mechanism model is proposed.

Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

The ability to learn from few examples, known as one-shot learning, is a hallmark of human cognition. Hyperdimensional (HD) computing is a brain-inspired computational framework capable of one-shot learning, using random binary vectors with high dimensionality. Device-architecture co-design of HD cognitive computing systems using 3D VRRAM/CMOS is presented for language recognition. Multiplication-addition-permutation (MAP), the central operations of HD computing, are experimentally demonstrated on 4-layer 3D VRRAM/FinFET as non-volatile in-memory MAP kernels. Extensive cycle-to-cycle (up to 1012 cycles) and wafer-level device-to-device (256 RRAMs) experiments are performed to validate reproducibility and robustness. For 28-nm node, the 3D in-memory architecture reduces total energy consumption by 52.2% with 412 times less area compared with LP digital design (using registers as memory), owing to the energy-efficient VRRAM MAP kernels and dense connectivity. Meanwhile, the system trained with 21 samples texts achieves 90.4% accuracy recognizing 21 European languages on 21,000 test sentences. Hard-error analysis shows the HD architecture is amazingly resilient to RRAM endurance failures, making the use of various types of RRAMs/CBRAMs (1k ∼ 10M endurance) feasible.

TMD FinFET with 4 nm thin body and back gate control for future low power technology

A 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is proposed and demonstrated for the first time. The TMD FinFET channel is deposited by CVD. Hydrogen plasma treatment of TMD is employed to lower the series resistance for the first time. The 2 nm thin back gate oxide enables 0.5 V of Vth shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.

Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things

For the first time, a CO2 far-infrared laser annealing (CO2-FIR-LA) technology was developed as the activation solution to enable highly heterogeneous integration without causing device degradation for TSV-free monolithic 3DIC. This process is capable to implement small-area-small-load vertical connectors, gate-first high-k/metal gate MOSFETs and non-Al metal inter-connects. Such a far-infrared laser annealing exhibits excellent selective activation capability that enables performance-enhanced stacked sub-40nm UTB-MOSFETs (Ion-enhanced over 50 %). Unlike TSV-based 3D-IC, this 3D Monolithic IC enables ultra-wide-IO connections between layers to achieve high bandwidth with less power consumption. A test chip with logic circuits, 6T SRAM, ReRAM, sense amplifiers, analog amplifiers and gas sensors was integrated to confirm the superiority in heterogeneous integration of proposed CO2-FIR-LA technology. This chip demonstrates the most variable functions above reported 3D Monolithic ICs. This CO2-FIR-LA based TSV-free 3D Monolithic IC can realize low cost, small footprint, and highly heterogeneous integration for Internet of Things.

MoS 2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS 2 availability

A U-shape MoS2 pMOSFET with 10nm channel and poly-Si source/drain is demonstrated. The fabrication process is simple. Because the Si S/D serves as the nucleation seed for CVD MoS2 deposition, thin MoS2 is well deposited in the channel region any where over the fully scale oxide coated Si wafer. This is a big step forward toward a low cost multi-layer stacked TMD IC technology.

Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics

Resistive memory device (Memristor) is one of the candidates for energy-efficient nonvolatile memory and nonvolatile logics (nvLogics) in the applications of wearable devices, Internet of Things (IoT), cloud computing, and big-data processing. However, resistive RAM (ReRAM) and memristor-based nvLogics suffer limited performance and low yield due to process variations in transistors and resistance of memristor. This presentation discusses the design challenges in read circuits for high-speed, area-efficient, and low-voltage ReRAM and nvLogics. Memristor-based nvLogics, such as nonvolatile-SRAM (nvSRAM), nonvolatile flip-flops (nvFF), and nonvolatile TCAM (nvTCAM) are included in this presentation. Several silicon-verified solutions on read scheme and sense amplifiers are also discussed in this presentation.

First fully functionalized monolithic 3D+ IoT chip with 0.5 V light-electricity power management, 6.8 GHz wireless-communication VCO, and 4-layer vertical ReRAM

For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D⁺-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D⁺ UTB-MOSFETs (600μA/282μA@VG= ± 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO<inf>2</inf> far-infrared laser annealing (CO<inf>2</inf>-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D⁺IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D⁺ IoT chip.