Min-g Chen

Steep Slope and Near Non-Hysteresis of FETs With Antiferroelectric-Like HfZrO for Low-Power Electronics

The antiferroelectricity in HfZrO2 (HZO) annealed at 600 °C with an abrupt turn ON of FET characteristics with SSmin = 23 mV/dec and SSavg = 50 mV/dec over 4 decades of IDS is demonstrated. The near non-hysteresis is achieved with an antiferroelectric-like HZO due to a small remanent polarization and a coercive field. A feasible concept of coupling the antiferroelectric and ferroelectric type HZO are used for low-power electronics and the memory applications, respectively.

Sub-60mV-swing negative-capacitance FinFET without hysteresis

In this work, we report the first Negative-Capacitance FinFET. ALD Hf042Zr058O2 is added on top of the FinFETs gate stack. The test devices have a floating internal gate that can be electrically probed. Direct measurement found the small-signal voltage amplified by 1.6X maximum at the internal gate in agreement with the improvement of the subthreshold swing (from 87 to 55mV/decade). ION increased by >25% for the IOFF. For the first time, we demonstrate that raising HfZrO2 ferroelectricity, by annealing at higher temperature, reduces and eliminates IV hysteresis and increases the voltage gain. These discoveries will guide future theoretical and experimental work.

Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing

For the first time, a four-layer HfOx-based 3D vertical RRAM, the “tallest” one ever reported, is developed and integrated with FinFET selector. Uniform memory performance across four layers is obtained (±0.8V switching, 106 endurance, 104s@125°C). SPICE simulations show that high drive current of pillar select transistors is required for high-rise 3D RRAM arrays. The four-layer 3D RRAM is a versatile computing unit for (a) brain-inspired computing and (b) in-memory computing. (a) Stochastic RRAM synapses enable robust pattern learning for a 3D neuromorphic visual system. The 3D architecture with dense and balanced neuron-synapse connections provides 55% EDP savings and 74% VDD reduction (enhanced robustness) compared with conventional 2D architecture; (b) in-memory logic such as NAND, NOR, and bit shift, are essential elements for hyper-dimensional computing. Utilizing the unique vertical connection of 3D RRAM cells, these operations are performed with little data movement.

Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication

A sidewall electrode technology was successfully developed for the first time in this study, improving the understanding of the working mechanism in an ultra small, functional HfO₂-based resistive random access memory (RRAM) device (<; 1 × 3 nm²). This technology exhibits potential for application in atomic-scale memories. The 1 × 3 nm² RRAM device exhibited an excellent performance, featuring a high endurance of more than 10⁴ cycles, a large on/off verified window (>100), and reasonable reliability (stress time > 10³ s, 2 × 10⁴ h at 250 °C). Furthermore, the 1 × 3 nm² RRAM device exhibited distinctive unipolar behavior when a high voltage and rapid switching operation (7 V, 50 ns) were applied, and a switching mechanism model is proposed.

A sensitive and selective magnetic graphene composite-modified polycrystalline-silicon nanowire field-effect transistor for bladder cancer diagnosis

In this study, we describe the urinary quantification of apolipoprotein A II protein (APOA2 protein), a biomarker for the diagnosis of bladder cancer, using an n-type polycrystalline silicon nanowire field-effect transistor (poly-SiNW-FET). The modification of poly-SiNW-FET by magnetic graphene with long-chain acid groups (MGLA) synthesized via Friedel-Crafts acylation was compared with that obtained using short-chain acid groups (MGSA). Compared with MGSA, the MGLA showed a higher immobilization degree and bioactivity to the anti-APOA2 antibody (Ab) due to its lower steric hindrance. In addition, the magnetic properties enabled rapid separation and purification during Ab immobilization, ultimately preserving its bioactivity. The Ab-MGLA/poly-SiNW-FET exhibited a linear dependence of relative response to the logarithmical concentration in a range between 19.5pgmL(-1) and 1.95µgmL(-1), with a limit of detection (LOD) of 6.7pgmL(-1). An additional washing step before measurement aimed at excluding the interfering biocomponents ensured the reliability of the assay. We conclude that our biosensor efficiently distinguishes mean values of urinary APOA2 protein concentrations between patients with bladder cancer (29-344ngmL(-1)) and those with hernia (0.425-9.47ngmL(-1)).

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

FinFET With High-

We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO₂ high-κ spacer and compare it with its counterpart having SiO₂ low-κ spacer. The HfO₂ spacer structure reduces series resistance in the underlap regions due to the large capacitive coupling between the gate and the underlap regions. Both drain current and transconductance of p-channel FinFET are higher than those of the SiO₂ spacer device by about 3× when biased in the saturation region, and about 1.6× and 2×, respectively, when biased in the linear region. Subthreshold swing and drain-induced barrier lowering are also improved by incorporating the HfO₂ spacer.

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The ability to learn from few examples, known as one-shot learning, is a hallmark of human cognition. Hyperdimensional (HD) computing is a brain-inspired computational framework capable of one-shot learning, using random binary vectors with high dimensionality. Device-architecture co-design of HD cognitive computing systems using 3D VRRAM/CMOS is presented for language recognition. Multiplication-addition-permutation (MAP), the central operations of HD computing, are experimentally demonstrated on 4-layer 3D VRRAM/FinFET as non-volatile in-memory MAP kernels. Extensive cycle-to-cycle (up to 1012 cycles) and wafer-level device-to-device (256 RRAMs) experiments are performed to validate reproducibility and robustness. For 28-nm node, the 3D in-memory architecture reduces total energy consumption by 52.2% with 412 times less area compared with LP digital design (using registers as memory), owing to the energy-efficient VRRAM MAP kernels and dense connectivity. Meanwhile, the system trained with 21 samples texts achieves 90.4% accuracy recognizing 21 European languages on 21,000 test sentences. Hard-error analysis shows the HD architecture is amazingly resilient to RRAM endurance failures, making the use of various types of RRAMs/CBRAMs (1k ∼ 10M endurance) feasible.

Spacers for Improved Drive Current

A 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is proposed and demonstrated for the first time. The TMD FinFET channel is deposited by CVD. Hydrogen plasma treatment of TMD is employed to lower the series resistance for the first time. The 2 nm thin back gate oxide enables 0.5 V of Vth shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.

Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

Polysilicon nanowire (poly-Si NW) based biosensor is integrated with the wireless acquisition circuits in a standard CMOS SoC for the first time. To improve detection quality, a chopper DDA-based analog front-end with features of low noise, high CMRR, and rail-to-rail input range is implemented. Additional temperature sensor is also included to compensate temperature drift of the biosensor. The results indicate that the detection limit is as low as 10fM. The capability to distinguish one base-pair mismatched DNAs is also demonstrated.