Kailash Chandrashekar

A 2.4-GHz 20–40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

A digital outphasing transmitter is presented for 2.4-GHz WiFi. The transmitter consists of two delay-based phase modulators and a 26-dBm integrated switching class-D power amplifier. The delay-based phase modulator delays incoming LO edges with a resolution of 1.4 ps (8 bit) required to meet WiFi requirements. A phase MUX architecture is proposed to implement switching between phases once every LO period (2.4 GHz) without generating detrimental glitches at the output. Due to its open-loop nature, the proposed phase modulator is capable of delivering wide OFDM bandwidths up to 40 MHz. The paper analyzes the impact of impairments, e.g., delay mismatch within the delay cells and outphasing mismatches, as well as associated mitigation techniques. The transmitter has been implemented in a 32-nm digital CMOS process and delivers an OFDM average power of 20 dBm with an overall system efficiency of 18.6% when transmitting 54-Mb/s 64QAM signal. The fully digital design is expected to further improve in power dissipation and chip-area with further CMOS scaling.

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS

Integration of radios in SoCs along with digital baseband and application processors is desirable for cost and form-factor reasons. Digital processors are typically implemented in the latest CMOS process to take advantage of the increased density and performance afforded by CMOS scaling. Integration of traditional RF circuits, however, requires accurate RF and passive models that typically lag behind digital transistor models by several quarters. This makes RF integration the limiting factor for time-to-market for the whole SoC, or results in sub-optimal multiple-chip solutions. Furthermore, traditional RF circuits do not benefit from scaling as digital circuits do, e.g. due to extensive use of inductors, the ever-lowering supply voltage, etc. This work presents a digital WiFi transmitter (TX) implemented in a 32nm digital CMOS process to address these issues. An outphasing architecture allows implementation of both amplitude and phase modulation using scaling-friendly, delay-based, switching phase modulators. The integrated PA was already shown to be possible to design with no RF models [1]; known issues of outphasing PA design (e.g. output impedance modulation, linearity, efficiency) are also addressed in [1]. The phase modulator uses an open-loop architecture to accommodate OFDM bandwidths up to 40MHz. The TX achieves state-of-the-art performance already in 32nm and is moreover expected to: (1) improve with scaling and (2) port easily over successive process nodes.

A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management

A VCO used in a PLL inside a wireless transceiver can be sensitive to interference from other radio circuitry (e.g. on-chip PA), components of the SoC system (e.g. clocks and their harmonics) and nearby radios. To prevent VCO pulling by the PA, fractional dividers can be used to offset the VCO frequency (fVCO) with respect to the PA. Multistandard radios covering, for example, WiFi 2.4 to 2.5GHz and 5 to 5.8GHz, and WiMAX 2.3 to 2.7GHz and 3.3 to 3.8GHz, may require multiple VCOs and/or multiple fractional dividers to cover all bands [1], resulting in complexity and area overhead. This paper proposes a versatile reconfigurable fractional divider capable of covering the above standards with a single VCO with 20% tuning range. The divider is all-digital, hence scaling-friendly, and uses digital calibration to eliminate the need for filtering and area-intensive inductors. The versatility afforded by the reconfigurable fractional divider allows for the transceivers LO generation (LOG) frequency plan to be adjusted on-the-fly. This can avoid VCO pulling from interferers which may not be known a-priori, like SoC-CPU clocks that are adjusted dynamically for best performance.

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

A 6-bit time-to-digital converter that achieves mismatch free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for WiFi/WiMax radios. The TDC consumes 3 mW from a 1.05-V supply and occupies an area of 0.004 mm2. A digital frequency-locked loop is used to track and correct for PVT variations in the TDC and no additional linearization or mismatch calibrations are required. The DPLL uses a 20-bit high dynamic range DAC to drive a VCO in order to effectively realize a DCO with 100-Hz frequency resolution. The 2.5-GHz WiFi band LO output is generated from a 40-MHz reference with an integrated phase noise of - 35 dBc (10 kHz to 10 MHz) while consuming 21 mW . The worst case spur in the LO output is below - 50 dBc without requiring TDC mismatch and linearity calibration.

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS

A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3.

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications

To benefit from Moores law and minimize form-factor and active power consumption, digital-rich SoCs should be integrated in the most advanced technology node. If the transceiver is integrated in a different technology node, multi-chip solutions are required, increasing system cost and form-factor. Traditional radio architectures require extensive use of high-quality passives, which might use large silicon area or not be available due to process limitations. Fast time to market also demands quicker design cycles, where extensive use of standard digital cells and even automated place-and-route tools for layout is preferred [1]. The proposed transmitter leverages a polar architecture with synthesized digital-to-time converter (DTC) wideband phase modulator, an all-digital PLL and a digital PA with matching network implemented on a flip-chip package to enable single-chip integration in 14nm trigate/finFET technology for IoT and wearable SoCs.

A 32nm, 0.65–10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O

In CPU, SOC, GPU, and PC-on-chip, I/O power consumption can be significant. To improve power efficiency, I/O bundles in group of 4, 8, or 16b, should scale their data rate according to the application requirements. However, clocking architecture imposes significant challenges to support different data rate simultaneously. In high bandwidth I/O, LC oscillators are preferred for low jitter, but the limited frequency range confines the data rate tuning. Multiple LC-PLLs are costly in area and power, and sometimes infeasible due to heavily congested I/O area. Worse still, couplings between inductors could lead to PLL pulling closing the sampling eye. In this paper, a reconfigurable 0.65–10GHz digital fractional-n clock generator using a single LC PLL, calibrated 0.75/1.25/1.75 digital fractional post dividers for serial I/O is presented. The architecture enables I/O driven by the same PLL to operate at different data rate, thereby reducing power. In addition, multiple LC-PLLs are replaced by one saving area, power, and coupling between LC oscillators. The PLL incorporates a staggered varactor, wide-tuning VCO, and a hysteretic redundant frequency acquisition for improved temperature stability. The prototype in a 32nm high-k metal gate process has a measured TX/RX jitter of 0.9/0.3 ps/σ and dissipates 36.2mW from 1.05V supply.

A digital fractional-N PLL with a 3mW 0.004mm 2 6-bit PVT and mismatch insensitive TDC

In this paper, a 3mW 0.004mm2 6-bit time-to-digital converter (TDC) is presented. By re-using a single delay cell and sampling flip-flop (FF), mismatch free operation is achieved. PVT variations are tracked and corrected by a digital frequency lock loop (DFLL). The proposed TDC is demonstrated in a digital fractional-N PLL for WiFi/4G radios. A 20-bit high dynamic range (DR) digital-to-analog converter (DAC) drives the VCO to achieve 100Hz resolution. The PLL is fabricated in 32nm digital SoC CMOS with a flip-chip BGA package. The PLL produces a 2.5GHz band LO output with -35dBc integrated phase noise (10kHz to 10MHz) and the worst case spur less than -50dBc while consuming 21mW.