Paolo Madoglio

Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL

This paper presents the design of a time-to-digital converter (TDC) suitable for a 3.5-GHz all-digital phase-lock loop (PLL). The converter is based on a digital bang-bang delay-lock loop, which allows constant resolution over process and temperatures spreads, avoids an off-chip filter and guarantees fast lock. The clock rate of the digital filter is scaled down by eight from the 3.5-GHz input to allow its implementation with standard cells. The occurrence of a limit cycle is analytically predicted and properly minimized, and its effect on the PLL phase noise is discussed. The circuit fabricated in 90-nm CMOS entails 16 delay stages, which lock to the input frequency in the 2.9-3.9-GHz range (limited by the available signal source). The delay of each TDC cell can be controlled with 50-fs step and the TDC time resolution is 16 ps at 3.9 GHz. The power consumption ranges between 8.1 and 16.5 mW, respectively. The limit-cycle-induced spur is below - 50 dBc. The area occupation is 0.032 mm2.

A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS

Local-oscillator (LO) pulling is a typical issue in fully integrated transceivers. To offset the oscillator frequency from the PA output frequency, SSB mixing or division-by-2 is typically used [1]. However, the first might require additional filtering to remove mixing spurs and the latter is still sensitive to second-harmonic pulling. The divider described in this paper prevents LO pulling by introducing a fractional ratio between input and output frequencies. Since fractional spurs are suppressed by digital calibration, no additional filtering is required, removing inductors and saving silicon area.

AD-PLL for WiMAX with digitally-regulated TDC and glitch correction logic

This paper describes the design of an All-Digital Phase Locked Loop (AD-PLL) for wireless applications in the WiMAX 3.3–3.8 GHz bandwidth. The time/digital converter (TDC) sets the in-band noise and it may be responsible for the presence of spurious tones at the PLL output. The TDC is implemented as a delay-locked loop (DLL) to be insensitive to process spreads and it uses a lead-lag phase detector and a digital loop filter to further take advantage of the digital approach. The most important source of spurs is identified in the time skew between counter and TDC in the PLL. This mechanism gives rise to a glitch in the digital feedback signal and spurs in the output spectrum. A simple glitch-corrector logic is described, that completely removes this effect, thus allowing to meet the phase noise specifications. The AD-PLL has been designed in a 90 nm CMOS process.