Kamal K. Sikka

Analysis and optimization of a natural draft heat sink system

An analytical solution for a system consisting of a vertical, parallel-plate, isothermal heat sink, and a chimney is presented. The result is applied to problems in which the size of the overall system is constrained. A ridge of maximum total heat transfer is observed with respect to the plate spacing and heat-sink height. The ridge suggests that heat-sink height may be reduced without diminishing the thermal performance for natural draft cooling. The flow characteristics of optimal systems reveal that systems with and without chimneys dissipate maximum heat when the velocity profiles within the heat sink are fully developed and developing, respectively.

Heat sinks with fluted and wavy plate fins in natural and low-velocity forced convection

The effect on heat transfer of geometrically rearranging the surface area of a finned heat sink is investigated. Novel heat sinks with fluted and wavy plate fin configurations are designed and fabricated together with conventional longitudinal-plate and pin fin heat sinks. The experimental apparatus, consisting of the guard heater assembly, isolation chamber, wind tunnel, and data acquisition instrumentation, is described. The thermal performance of the novel and conventional heat sinks is measured and compared for the horizontal and vertical base plate orientations under natural and low-velocity forced convection conditions. Results, presented as the Nusselt number against the Rayleigh or Reynolds numbers, reveal that the pin fin heat sink generally outperforms the other heat sinks, when the heat sink surface area is held constant. A significant effect on heat transfer of the orientation of the forced flow with respect to the buoyancy flow is observed. Overall, the novel heat sink designs do not yield significantly better thermal performance than an optimized conventional longitudinal-plate heat sink.

An analytical temperature prediction method for a chip power map

An analytical method is presented for predicting the chip temperature for a chip-on-spreader geometry with a nonuniform power distribution. The analytical method applies the principle of linear superposition to a known exact solution for heat spreading in the spreader together with the addition of one-dimensional heat transfer resistances through the chip and thermal interface material. The results of the analytical method are compared to numerical results with good accuracy for two geometric cases and three power maps. Implementation in a spreadsheet makes the analytical method easy-to-use and should allow for rapid prediction of chip temperature distributions in the early design stages for power map optimization.

Organic substrates for flip-chip design : A thermo-mechanical model that accounts for heterogeneity and anisotropy

Abstract We present a thermo-mechanical characterization of organic substrates that accounts for heterogeneity both in the in-plane and out-of-plane directions. Systematic observation of the board files of a number of substrates of commercial interest reveals primarily three recurrent topological arrangements of copper and polymer; for each arrangement, the in-plane effective thermo-elastic properties are calculated via appropriate composite materials models. The averaging process in the out-of-plane direction (i.e. the stacking effect) is performed using standard laminated plate theory. The model is successfully applied to various regions of three organic substrates of interest (mainly differing in core thickness): the analytically calculated effective Young’s moduli ( E ) and coefficients of thermal expansion (CTE) are shown to be typically within 10% of the experimental measurements. An important attribute of this model is its ability to provide substrate description at various levels of complexity: a few effective properties are outputted that can be useful for further purely analytical investigations; at the same time, the model provides the full stiffness matrix for each region of the substrate, to be used for more detailed finite elements simulations of higher-level structures (e.g. silicon die/underfill/substrate/cooling solution assemblies). Preliminary application of this model to the warp analysis of a flip-chip is presented in the end.

An efficient lid design for cooling stacked flip-chip 3D packages

3D chip-stack packages are more difficult to cool than 2D chip packages due to additional thermal resistances in the heat flow path. The additional thermal resistances are due to the presence of the C4 joins between the chips, the BEOL wiring layers in each chip and the silicon thickness of the chips in the stack. In this paper we present an efficient lid design for a 3D flip-chip package that allows contact, through a thin thermal interface material (TIM) layer, of exposed chip regions of the lower chips in the 3D vertical stack. The efficient lid was assembled on to 3D thermal test vehicle packages and its thermal advantage over standard lid 3D packages was experimentally demonstrated. The packages were cross-sectioned to ensure that the assembly process yielded the correct TIM gaps. A thermal conduction model was calibrated to the experimental data and the stacked chip-chip and the efficient lid TIM thermal resistances were extracted from the model. A sensitivity analysis was then conducted to identify the important parameters controlling the thermal performance of the 3D package.

Modeling of vapor chamber as heat spreading devices

As the heat density on the chip increases and heat dissipation is more localized, there are growing interests in developing alternative heat spreading devices. Vapor chambers have been used as heat spreading devices in heat sink bases. Before considering for integration into package heat spreaders or lids, the compatibility of the vapor chamber with the assembly processes would have to be assessed. However, before embarking down that path, this paper attempts to quantify the thermal benefit, if any, of vapor chamber heat spreaders compared to commonly used solid metal heat spreaders. A thermal model has been developed consisting of a heated chip integrated with a substrate, thermal interface material, vapor chamber lid and heat sink. The vapor chamber is represented by multiple block layers with effective thermal conductivities. It is revealed that the model can predict the temperature profile fairly well as compared with the results of a detailed numerical model. A sensitivity study shows that the thermal performance is sensitive to the effective thermal conductivity of the wick structure and insensitive to the effective thermal conductivity of the vapor space. A parametric study indicates that the vapor chamber heat spreader out-performs a copper block of the same dimension when the footprint size is larger than a certain value. It is concluded that vapor chamber is most effective in spreading heat over large areas. Consequently, it is suitable for applications where more surface area is desired due to reasons such as low heat transfer coefficients

Effects of package orientation and mixed convection on heat transfer from a PQFP

The thermal resistance of a surface-mount, plastic quad flat package (PQFP) was measured over a range of heating powers, air velocities, and package orientations. The specific package was one developed by a Joint Electronic Device Engineering Council (JEDEC) committee for standardized testing. The package was mounted in a low-speed wind tunnel which could be rotated in a vertical plane, thus changing the orientation of the package with respect to the gravity vector. Results define the limits of mixed convection for a horizontal package, and of orientation effects for package/tunnel orientations from buoyancy-opposing to buoyancy-assisting. For large air velocities greater than 2.5 m/s, for all tunnel orientations, the package thermal resistance shows a steep decrease, which is attributed to restarting of the surface boundary layer on the package.

Thermal modeling for warpage effects in organic packages

INTRODUCTION Maintaining the integrity of the heat dissipation path for high end microelectronic devices has become increasingly challenging as the industry migrates from ceramic to organic packaging. Typically, flip chip organic packages undergo significant thermal and mechanical stresses throughout the manufacturing process, including chip join, underfill, encapsulation, BGA attach and card join. As a result of the mismatch of thermal and mechanical properties between the components, significant warpage is generated in the organic substrate, the chip, and the thermal interface material (TIM1) on completion of the assembly. Warpage affects not only the substrate coplanarity but also the thermal performance of the TIM1. At room temperature, the center of an adhesive TIM1 is under compression between the lid and chip while the corners and edges are under tensile stress. The effective thermal conductivity for the portions of the TIM1 under tensile stress can be significantly lower due to the elongation of the gap and the narrowing of the heat flow area. The present paper describes an approach to model the thermal performance of an adhesive thermal interface material taking into account the warpage effects and the inherent out-of-flatness in the heat spreader. Reasonable agreement is obtained between the modeling results and thermal measurements for a representative thermal test vehicle. The present modeling approach can potentially be used to optimize the component design and the bond and assembly process to achieve optimum thermal performance.

Package cooling designs for a dual-chip electronic package with one high power chip

Dual-chip microelectronic packages (DCP) with one high power chip are being increasingly encountered in computer and other electronic systems where a common chip carrier, whether a ceramic or an organic laminate, has a central processing unit (CPU) accompanied by a memory chip. In this study, package cooling designs are developed and presented for cooling two product applications of the DCP, with one application having larger power dissipation on the CPU compared to the other. Thermal analysis was conducted to identify the encapsulation solutions for the DCP. Mechanical analysis was then conducted to identify any structural integrity concerns and include appropriate verification tests during reliability assurance testing. The encapsulation processes were optimized to ensure the reliability of the package under field operation. The reliability of the packaging structures was assured using thermal measurements, acoustic sonography, and shear and tensile strength measurements of using test vehicles and actual product DCPs.

Using cap-integral standoffs to reduce chip hot-spot temperatures in electronic packages

For high-power electronic packages, chip hot-spots and cross-chip temperature gradients represent a significant portion of the total thermal resistance from chip to ambient. This paper presents a technique of reducing the chip hot-spot temperatures using cap integral standoffs. The thermal benefit of the standoffs is shown experimentally and validated using thermal modeling. Thermal modeling is then extended to non-uniform power dissipation chips. Results show that the chip hot-spot temperature can be reduced by 5-10 /spl deg/C in a 100 W electronic package.