Sushumna Iruvanti

High thermal conductivity epoxy-silver composites based on self-constructed nanostructured metallic networks

We demonstrate epoxy-silver nanoparticle composites with high thermal conductivity κ enabled by self-constructed nanostructured networks (SCNN) forming during the curing process at relatively low temperatures (150 °C). The networks formation mechanism involves agglomeration of the polyvinylpyrrolidone (PVP) coated nanoparticles, PVP removal, and sintering of the nanoparticles at suppressed temperatures induced by their small diameters (20–80 nm). Sintering and the SCNN formation are supported by differential scanning calorimetry and electron microscopy investigations. The formation of SCNN with high aspect ratio structures leads to enhancements in the measured thermal conductivity κ of the composite by more than two orders of magnitude versus the pure epoxy. However, κ enhancements are modest if microparticles (1.8–4.2 μm) are employed instead of PVP coated nanoparticles. The κ trends are qualitatively explained using a percolating threshold thermal conductivity model for the microcomposites. For the nano...

An advanced multichip module (MCM) for high-performance UNIX servers

In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

A power, packaging, and cooling overview of the IBM eServer z900

This paper provides an overview of the power, packaging, and cooling aspects of the IBM eServer z900 design. The semiconductor processor chips must be supported and protected in a mechanical structure that has to provide electrical interconnects while maintaining the chip junction temperature within specified limits. The mechanical structure should be able to withstand shock and vibrations during transportation or events such as earthquakes. The processor chips require electrical power at well-regulated voltages, unaffected by the ac-line voltage and load current fluctuations. The acoustical and electromagnetic noise produced by the hardware must be within the limits set by national regulatory agencies, and the electronic operations must be adequately protected from disruption caused by electromagnetic radiation. For high availability, the power, packaging, and cooling hardware must have redundancy and the ability to be maintained while the system is operating. This paper first overviews the packaging hardware, followed by a description of the first- and second-level packaging, which includes the mother board and the multichip module. Thermal management is discussed from the point of view of both the multichip module and the overall system. Power conversion, management, and distribution are presented next. Finally, the design aspects involved with meeting the requirements of electromagnetic compatibility, acoustics, and immunity to shock, vibration, and earthquakes are discussed.

Development of a Low CTE chip scale package

This paper describes the development of a low CTE organic Chip Scale Package (CSP) jointly by KST and IBM. Tests carried out on the low CTE laminate material and subsequently on the related CSP are described. The new material set, identified as Advanced SLC Package, combines low CTE core and build-up dielectric materials to achieve a composite laminate CTE of 9-12 ppm/°C, which is intermediate between the CTEs of silicon device and conventional board. The lower composite CTE reduces the dimensional mismatch between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI) and white bumps. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. Global and chip-site warp data from thermo-mechanical modeling are compared to the measured warp data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated.

Predicting thermo-mechanical degradation of first-level thermal interface materials (TIMs) in flip-chip electronic packages

Ensuring adequate thermal performance is essential for the reliable operation of flip-chip electronic packages. Thermal interface materials (TIMs), applied between the die and a heat spreader form a crucial thermal junction between the first level package and external cooling mechanisms such as heat-sinks and cooling fans. Selection of a good TIM is dependent not only on its thermal properties but also on its ability to withstand mechanical stresses in an electronic package. In the past, FEM models have been applied to obtain the stresses and strains in the TIM using time-independent analysis. However, there has only been limited work in extending these models to predict the damage (both mechanical and thermal) in a TIM during thermo-cyclic loading. Our current work presents a technique to predict the thermal damage in TIMs over cyclic loading. Calibrated finite element analysis models have been created to predict accurate TIM strains in thermal test-vehicles. These predicted mechanical strains are then correlated with experimentally observed thermal degradation and finally, a phenomenological model is developed which predicts the thermal performance of an electronic package during cyclic loading.

Delamination mechanisms of thermal interface materials in organic packages during reflow and moisture soaking

A thermal interface material (TIM) is typically a compliant material with high thermal conductivity that is applied between a heat-generating chip and a heat spreader in an electronic package. For a high-conductivity polymeric TIM, the adhesion strength between the TIM and its mating interfaces is typically weak, making the TIM susceptible to degradation when subjected to environmental stresses. At typical chip operating temperatures which are below the curing temperature of the TIM, a compressive force acts on the TIM at the chip center due to the CTE mismatch between the die and the organic chip carrier. Conversely at high BGA(Ball Grid Array) or card-attach reflow temperatures, the TIM center is under tension and the TIM tends to either cohesively separate or adhesively separate from the interfaces. Also, during moisture soaking, such as 85C/85%RH, the organic chip carrier absorbs moisture and expands. The hygroscopic expansion of the organic chip carrier is of the same order of magnitude as the thermal expansion. This expansion reduces the compressive force acting on the TIM, and for certain package constructions, this can lead to degradation of thermal performance. In this paper, the delamination mechanism of a polymer-based thermal interface material in an organic package during reflow and moisture soaking is investigated. The in-situ deformation of the TIM bondline was measured by a digital image correlation (DIC) method on a cross-sectioned part. The TIM bondline deformation was also captured by a digital camera. The coefficients of thermal expansion and hygroscopic expansion for different organic materials were measured, and a finite element analysis of the hygroscopic expansion and TIM bondline deformation was conducted. The affect of T&H stress was analyzed using an equivalent CTE concept.

Gap-reduced thermal paste package design for cooling single flip-chip electronic modules

A method of reducing the thermal paste chip-to-cap interface gap is presented to achieve enhanced cooling of single flip-chip electronic modules. The structure and assembly process steps of the gap reduction design are described. The thermal reliability of the design is evaluated by measuring the thermal resistance for several permutations of the structural design variables, allowing identification of an optimum design configuration.

Multi-chip package thermal management of IBM z-server systems

The recently announced IBM z9 server system presents unique cooling requirements from a packaging perspective. Cooling has to be achieved for sixteen chips mounted on a common glass ceramic chip carrier. Eight of the sixteen chips dissipate significant power. A recently described small gap technology (SGT) is used to attain customized chip to cap gaps. An advanced thermal compound (ATC) is used as the interface between the chips and the cap. The package thermal and mechanical design is first described. Design optimization is achieved by detailed finite element thermo-mechanical modeling. The complex encapsulation process to attain the correct chip to hat ATC gaps is outlined. Verification of the ATC gaps is an integral part of the assembly process. The reliability qualification is then discussed. Issues found during the qualification were the structural fragility of the glass ceramic chip carrier flange and ATC thermal degradation. The structural robustness of the chip carrier was improved by modifying its design. ATC degradation is quantitatively related to the shear strain

Engineered thermal interface material

The power dissipation and device junction temperature control in high end processors, stacked and hybrid packages, test and burn-in systems, LED devices, etc. present challenges in cooling. Many types of consumer devices and sensors are proliferating. All these applications require an ongoing improvement in thermal management. A key aspect of electronic package cooling is the thermal interface material used between the heat generating component and the heat spreader or heat sink. High performance thermal interface materials enable Tj reduction, device performance improvement and/or lower power operation. Organic laminate packages are especially vulnerable to package failures driven by CTE mis-match driven stresses and strains. Choice of TIM is therefore critical in addressing not only the thermal challenges, but also the mechanical weaknesses of a laminate package. Often a polymeric TIM with adequate compliance to address the mechanical issues and yet having a high thermal performance is desired. The properties of the TIM, such as the modulus, elongation, adhesion to both surfaces and thermal impedance, have to be carefully selected for optimum performance in a package. In this paper, we report the development of an industry leading, high performance thermal interface material. The project involved engineering the matrix polymer properties to systematically vary the composite modulus and die shear strength and meet the desired TIM property objectives. Methodical material property characterizations were carried out for feedback and formulation improvement. A few formulations were developed with TIM1 impedance in the range of 0.04-0.07 cm2C/W. The thermal performance was measured on thermal test vehicles. Material and process parameters were investigated to minimize voiding. Material characterization and thermal performance results are presented in this paper.

Effect of Temperature Cycling and High Temperature Aging on the Elastic Properties and Failure Modes of Thermal Interface Materials

Highly filled thermally conductive silicone gels are routinely used as first level thermal interface materials (TIMs) between the die and lid, in flip-chip organic packages. The main challenge for these TIMs is overcoming the Coefficient of Thermal Expansion (CTE) mismatch between the die and lid materials. The TIMs must maintain excellent adhesion to both the die and lid surfaces in order to achieve and maintain optimal thermal performance. The CTE mismatch leads to increased mechanical stress and degradation of the TIM, which in turn degrades the thermal performance. In this work, the effective modulus of several TIMs was calculated by finite element modeling (FEM) in concert with mechanical testing of thin bond-line aluminum-TIM sandwiches subjected to varied stress conditions. These results are correlated to the corresponding stress die shear testing and the impact on package performance is analyzed.Copyright