Jamil A. Wakil

Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements

An experimental technique is presented, which allows for spatially-resolved imaging of microprocessor power (SIMP). In a first step this method utilizes infrared (IR) thermal imaging, while the processor is effectively cooled using an IR-transparent heat sink. In the second step the underlying power distribution is derived by determining the temperature fields for each individual power source on the chip. The measured chip temperature distribution is represented as a superposition of these temperature fields. The SIMP data reveals significant temporal and spatial variations of the microprocessor power/temperature distribution, which can be attributed to the circuit layout as well as to the varying utilization levels across the processor while running full workloads. In this paper we have applied the SIMP method to the dual core PowerPCtrade970MP microprocessor to measure detailed temperature and power distributions under full operating conditions. In the first part of the paper the impact of power and temperature limitations of high performance CMOS chips is discussed in detail, where we distinguish between hotspot-limited (or temperature-limited) and power-limited chips. The discussion shows the importance of temperature and power distributions for chip floor planning, layout, design and architecture. Second, we present the experimental details of the SIMP method, which is applied to the dual core PowerPC970MP to directly measure the temperature and power fields as a function of workload and frequency. A pronounced movement of the hotspot location is observed. Finally, the hotspot of a competitive microprocessor is compared by measuring temperature efficiencies (temperature increase/performance) for the same workloads and cooling conditions

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

A practical implementation of silicon microchannel coolers for high power chips

The paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance of 10.5 C-mm/sup 2//W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of less than 35 kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300 W/cm/sup 2/. Coolers of this design should be able to cool chips with average power densities of 400 W/cm/sup 2/ or more.

Spatially-resolved imaging of microprocessor power (SIMP): hotspots in microprocessors

In this paper we present the details of a new technique, which allows for spatially-resolved imaging of microprocessor power (SIMP) under full operational conditions. The method involves two steps: In the first step it utilizes infra-red (IR) thermal imaging, while an IR-transparent coolant flows through a specially designed cooling cell directly over the microprocessor. In the second step the underlying power distribution is derived by determining the temperature fields for each individual power source on the chip. The measured chip temperature distribution is then represented as a superposition of these temperature fields. The SIMP data reveals significant temporal and spatial variations of the microprocessor power/temperature distribution, which can be attributed to the circuit layout as well as to the varying utilization levels across the processor while running real workloads. More specifically, strong non-uniformities or hotspots in the microprocessor power distributions are observed, which have significant implications for packaging and cooling designs

Thermal performance impacts of heat spreading lids on flip chip packages: With and without heat sinks

Abstract Heat spreading lids on a flip chip package can provide many thermal and mechanical advantages. Major drawbacks are higher module costs and potentially poorer thermal performance with a heat sink. This study compares thermal performance of direct lid attach (DLA) and bare die flip chip packages and addresses the roles of interface resistance and lid thickness. The IBM SLC TM package is tested and modeled. JEDEC standard wind tunnel tests as well as CFD models are used for analysis. The study reveals that the DLA design without additional heat sinking can provide significantly better thermal performance compared to the bare die package, depending on package size and airflow rate. With a heat sink the performance of the lidded package can be superior or inferior depending on interface resistance, lid design and the standard used for comparison.

Measurement of microbump thermal resistance in 3D chip stacks

The thermal resistance of Pb-free ~25 μm diameter microbumps with pitches of 50, 71, and 100 μm has been measured with and without underfill in four high chip stacks. With underfill, the unit thermal resistance values were 8.0, 15.5, and 19.0 C-mm2/W for 50, 71, and 100 μm pitch microbumps, respectively. The average microbump height was 16.1 microns. For the 50 μm pitch case, the thermal conduction through the underfill is roughly equal to that of the microbumps alone.

An efficient lid design for cooling stacked flip-chip 3D packages

3D chip-stack packages are more difficult to cool than 2D chip packages due to additional thermal resistances in the heat flow path. The additional thermal resistances are due to the presence of the C4 joins between the chips, the BEOL wiring layers in each chip and the silicon thickness of the chips in the stack. In this paper we present an efficient lid design for a 3D flip-chip package that allows contact, through a thin thermal interface material (TIM) layer, of exposed chip regions of the lower chips in the 3D vertical stack. The efficient lid was assembled on to 3D thermal test vehicle packages and its thermal advantage over standard lid 3D packages was experimentally demonstrated. The packages were cross-sectioned to ensure that the assembly process yielded the correct TIM gaps. A thermal conduction model was calibrated to the experimental data and the stacked chip-chip and the efficient lid TIM thermal resistances were extracted from the model. A sensitivity analysis was then conducted to identify the important parameters controlling the thermal performance of the 3D package.

Thermal modeling of on-chip interconnects and 3D packaging using EM tools

The green (low power) chip design demands dramatic thermal and electrical simulation capabilities. In this paper, a novel thermal simulation approach for automatic thermal modeling of very large problems is introduced. This methodology can be fully integrated with existing solvers for electrical simulations, and make it possible to analyze practical on-chip and packaging thermal problems using the existing electromagnetic tools and geometry definitions, with very small additional effort. Its various applications to BEOL (on-chip wiring), thermal guideline design, and 3D integration (for multiple chip stacks) thermal modeling are investigated in this paper. We will demonstrate this capability with an automatic modeling framework, ChipJoule, for representative cases.

Nonuniform temperature and strain fields in a powered package

This paper analyzes the nonuniform temperature and strain fields resulting from power dissipation in an electronic package. A 208 lead plastic quad flat pack (PQFP) manufactured by Texas Instruments is used to show the temperature distribution and mechanical deformation resulting from power dissipation in the package. The package is tested experimentally and thermally modeled using finite element analysis to obtain the temperature distribution in the active package. The moire interferometry technique is used to acquire displacement contours of an active PQFP and the results are compared to a uniformly heated sample. The results revealed that the thermal loading due to internal power dissipation produces significantly different strains than a uniformly heated sample.

Thermo-Mechanical Response of Thru-Silicon Vias Under Local Thermal Transients Using Experimentally Validated Finite Element Models

Significant research has focused on the reliability of through-silicon-vias (TSVs) under conventional uniform thermal loading conditions such as accelerated thermal cycling (0–100 C) or deep thermal cycling ( 40–125 C). This study analyzes the thermomechanical behavior of TSVs in 3D packages undergoing rapid local temperature fluctuations, as would be experienced in actual operation. A global=local finite element model is used to analyze the TSV behavior at various distances from the thermal fluctuation site. Transient thermal measurements, warpage and in-plane deformation measurements, as well as micro-Raman spectroscopy measurements are used to validate the model. The results reveal that the short term local temperature transients have minimal impact on the TSV stress state regardless of TSV location, implying that global packageinduced stresses dominate. [DOI: 10.1115/1.4004656]