Hilton T. Toy

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

An efficient lid design for cooling stacked flip-chip 3D packages

3D chip-stack packages are more difficult to cool than 2D chip packages due to additional thermal resistances in the heat flow path. The additional thermal resistances are due to the presence of the C4 joins between the chips, the BEOL wiring layers in each chip and the silicon thickness of the chips in the stack. In this paper we present an efficient lid design for a 3D flip-chip package that allows contact, through a thin thermal interface material (TIM) layer, of exposed chip regions of the lower chips in the 3D vertical stack. The efficient lid was assembled on to 3D thermal test vehicle packages and its thermal advantage over standard lid 3D packages was experimentally demonstrated. The packages were cross-sectioned to ensure that the assembly process yielded the correct TIM gaps. A thermal conduction model was calibrated to the experimental data and the stacked chip-chip and the efficient lid TIM thermal resistances were extracted from the model. A sensitivity analysis was then conducted to identify the important parameters controlling the thermal performance of the 3D package.

Package cooling designs for a dual-chip electronic package with one high power chip

Dual-chip microelectronic packages (DCP) with one high power chip are being increasingly encountered in computer and other electronic systems where a common chip carrier, whether a ceramic or an organic laminate, has a central processing unit (CPU) accompanied by a memory chip. In this study, package cooling designs are developed and presented for cooling two product applications of the DCP, with one application having larger power dissipation on the CPU compared to the other. Thermal analysis was conducted to identify the encapsulation solutions for the DCP. Mechanical analysis was then conducted to identify any structural integrity concerns and include appropriate verification tests during reliability assurance testing. The encapsulation processes were optimized to ensure the reliability of the package under field operation. The reliability of the packaging structures was assured using thermal measurements, acoustic sonography, and shear and tensile strength measurements of using test vehicles and actual product DCPs.

Gap-reduced thermal paste package design for cooling single flip-chip electronic modules

A method of reducing the thermal paste chip-to-cap interface gap is presented to achieve enhanced cooling of single flip-chip electronic modules. The structure and assembly process steps of the gap reduction design are described. The thermal reliability of the design is evaluated by measuring the thermal resistance for several permutations of the structural design variables, allowing identification of an optimum design configuration.

Silicon Microchannel Cooling for High Power Chips

In this work, single-phase Si microchannel coolers have been designed and characterized for cooling very high power density chips in single-chip modules (SCMs) in a laboratory environment. The average heat transfer coefficient was determined for a wide range of microchannel designs. Through the use of multiple heat exchanger zones and optimized cooler fin design, an average unit thermal resistance of 16.2°C·mm2/W between the chip surface and the inlet cooling water was demonstrated for an Si microchannel cooler attached to a chip with Ag epoxy in an SCM. Very good uniformity from SCM to SCM (±2%) and within an SCM (±5%) was achieved. Further, cooling of a thermal test chip with a microchannel cooler bonded to it and packaged in an SCM was also demonstrated for a chip power density greater than 400 W/cm2. Coolers of this design should be able to cool chips with average power densities of 500 W/cm2 or more.