Kamal Sahota

Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPS

The large commercial success of multiband multimode 3rd-generation cellular products has driven single-chip integration, SAW-filter reduction and low power consumption. State-of-the-art solutions require quad-band EGSM combined with multiband WCDMA/HSPA receiver diversity and integrated GPS. Compact form factors make single-chip SAW-less solutions highly desirable. A Quad-Band GSM/EDGE-only transceiver was published in [1], and Triple-Band WCDMA-only transceiver solutions were published in [2–4]. This work describes the first multiband WCDMA/HSPA/EGPRS single-chip transceiver with GPS and receiver diversity. This device supports UMTS Bands 1,2,3,4,5,6,8,9,10 and GSM/EDGE 800, 900, 1800, 1900MHz Bands. It is implemented in cost-effective 0.18µm RF CMOS technology and uses a reduced number of TX and RX SAW filters.

A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor

Cellular phones in emerging markets have continued to grow with multimedia features such as MP3 playback, video encode and decode, high-resolution cameras and web browsing. To efficiently support multimedia functionalities, highperformance modems are required. There is also a strong demand to reduce the cellular phone PCB footprint, and to enable integration of peripheral devices such as Bluetooth and Wireless LAN. Previously reported SoC or SiP solutions have integrated a GPRS/EDGE radio with modem and limited multimedia capabilities [1–4]. This paper presents a multimode UMTS/GSM RF transceiver integrated with a digital baseband having advanced multimedia functionalities. The SoC, designed in 65nm digital CMOS, supports quad-band GSM/GPRS/EDGE (3GPP R4, Class 12) and tri-band UMTS/WCDMA (3GPP R99, R5 cat 5/6), including band 1–2–4–5–6–8–9–10.

A low power CMOS SAW-less quad band WCDMA/HSPA/1X/EGPRS transmitter

In this paper we present a multi-band CMOS transmitter for cellular applications. The transmitter covers a wide range of frequency bands and it is designed to minimize power consumption in order to increase hand-set talk-time. The output noise performance allows the removal of SAW for certain W-CDMA and CDMA bands; moreover it can be configured to be used for SAW-less GSM/EDGE operations while maintaining an excellent linearity.

A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode Transceiver

This paper describes a GPS receiver circuit that operates simultaneously with WCDMA/CDMA2000 transceivers. This receiver uses a low-IF architecture to minimize the external passive components. The RF front-end circuit dynamically adjusts the linearity performance based on the instantaneous transmitting power of the integrated transmitter. The receiver measured performances are >80dB gain, 2.0dB noise figure, >20dB image rejection, maximum out-of-band IIP3 is +6dBm. The synthesize features -132dBc/Hz phase noise at 1MHz offset frequency and a total integrated double sideband phase noise of less than -30dBc in the 100Hz to 1MHz band. The receiver is fabricated in a 0.18 mum RFCMOS process, and draws 36.7mA at high linearity mode and 27.4mA at low linearity mode using switch mode power supply.

RF front end requirements for 3G and beyond

The cellular mobile terminals continue to evolve at a rapid pace from voice phones to Multi-band, Multi standard Multi-media devices of the future. The RF front end, of these devices continues to be more complex requiring many RF bands and Wireless standards to be supported in a single device. In addition, to support higher data rates multiple antennas and passive filters are required. Concurrency with other wireless standards puts additional constraints on passive filters, which are required to reduce the interference handling requirements of the RF transceiver. Innovation is needed in the components required in the RF front end such that the form factor, RF performance and power consumption is maintained to less complicated devices of the past, as more band and modes are added. This paper will discuss the key radio requirements of the RF front end in wireless devices.

A dual-band high efficiency CMOS transmitter for wireless CDMA applications

A dual-band transmitter integrated circuit (TxIC), including baseband filter and variable gain amplifier (VGA), upconverter, RF VGA, driver amplifier (DA), is implemented in 0.18 mum CMOS for CDMA applications. The TxIC increases the handset talk time dramatically with the PA-bypass feature. The chip provides more than a total power control range of 80 dB and a fine gain step of 0.25 dB/LSB. The chip achieves 52.3 dBc ACPR at +7 dBm output power with 52.2 mA and 51.7 dBc ACPR at +7 dBm output power with 51.9 mA for low band and high band applications respectively.

A base-band to RF BiCMOS transmitter RFIC for dual-band CDMA/AMPS wireless handsets

A single chip, base-band to RF, BiCMOS transmitter RFIC (RFT3100) for dual-band CDMA/AMPS wireless handsets is presented. The RFIC contains base-band I/Q modulator, UHF VCO buffer, IF PLL, VCO, IF and RF VGAs, image rejection RF upconverter, dual driver amplifiers for cellular and PCS bands, and a three wire serial interface to control the chip. The chip operates from a 2.7 to 3.3 V supply, a temperature range of -30 to 85/spl deg/C, and is packaged in a 32 lead 5/spl times/5 mm bump chip carrier (BCC) package. The chip is fabricated using a 18 GHz (analog NPN ft), 0.5 um BiCMOS process.

A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulation

A highly linear oscillator is presented for wideband polar modulation. It has both varactor voltage tuning for frequency locking and temperature compensation as well as inductive current tuning for linear phase modulation. Implemented in 65nm CMOS, it achieved a gain variation less than ±2% over more than 32MHz range meeting WCDMA polar modulation requirement. At 3.8GHz and 3MHz offset, its phase noise is -136.5dBc/Hz with current consumption of 18mA from 2.1V supply.

A CMOS Highly Linear Hybrid Current/Voltage Controlled Oscillator for Wideband Polar Modulation

A highly linear oscillator is presented for wideband polar modulation. It has both a varactor voltage tuning input for frequency locking and temperature compensation of phase locked loop (PLL) as well as an inductive current tuning input for linear phase modulation of PLL. Implemented in 65 nm CMOS technology, it achieved a frequency tuning gain variation of less than ±2% over more than 32 MHz frequency range meeting the WCDMA polar modulation requirement. At 3.8 GHz and 3 MHz offset, its phase noise is -136.5 dBc/Hz with current consumption of 18 mA from 2.1 V supply.

Tri-band SAW-less high linearity low noise CDMA receiver in 65nm CMOS

In this paper, the recent advances of CDMA receiver IC design are reviewed. Architecture choices for high linearity low noise CDMA receiver are compared in terms of cost, performance and complexity. The design of tri-band (450M/CELL/PCS) SAW-less CDMA receiver in 65nm CMOS is then described. Measured receiver noise figure is less than 3 dB, X-MOD IIP3 is better than 18 dBm for 450M/CELL band, and 8 dBm for PCS band, and IIP2 is better than 60 dBm for all the three bands.