Kamel Benaissa

RF CMOS on high-resistivity substrates for system-on-chip applications

The use of a high-resistivity substrate extends the capability of standard digital CMOS technology to enable the integration of high-performance RF passive components. The impact of substrate resistivity on the key components of RF CMOS for system-on-chip (SoC) applications is discussed. The comparison includes the transistor, transmission line, inductor, capacitor and varactor, as well as the noise isolation. We also discuss the integration issues including latch-up and well-well isolation in a 0.35-/spl mu/m Cu metal pitch, 0.1-/spl mu/m-gate-length RF CMOS technology.

0.1 /spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications

This paper describes the impact of substrate resistivity on the key components of the radio frequency (RF) CMOS for the system on chip (SOC) applications. The comparison includes the transistor, inductor, capacitor, noise isolation, latch-up as well as the well-to-well isolation in a 0.1 /spl mu/m (physical gate length) CMOS technology.

45nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors

Mobile system-on-chip (SoC) technologies require high-quality analog active and passive components along with low-power CMOS and dense SRAM. However, area scaling for both the SRAM bit cell and analog CMOS circuits is becoming increasingly difficult due to the impact of transistor random variation. To avoid added cost, co-optimizing the process for low random variation along with high performance and low power is required. We report a 45 nm lowpower technology with significantly reduced random variation for high yielding 0.255 mum2 SRAM arrays and analog transistors. Flexible RF and passive components for mobile SoCpsilas are also described. These process techniques enable continued 50% area scaling at 45 nm and beyond.

90 nm CMOS RF technology with 9.0 V I/O capability for single-chip radio

In this article, an industry leading 21 mask count 90nm CMOS SoC technology with integrated RF, analog, dense memory, low power or high-speed logic, and high-voltage DEMOS options is demonstrated. RF and analog characteristics with high on-chip voltage capability enable single chip radio design as well as many additional SoC applications.

New cost-effective integration schemes enabling analog and high-voltage design in advanced CMOS SOC technologies

We present novel and cost effective integration schemes with high performance analog and high voltage components to enable system-on-chip (SOC) designs in advanced CMOS technologies. The new transistors have superior analog performance compared to the standard logic devices resulting in significant area savings and greater analog functionality. The new high voltage (HV) transistors enable reliable 6V capability with high performance for direct battery connection circuits and other high voltage applications. Additional cost-free components are also provided including fully isolated CMOS; ppoly-pwell capacitors and varactors; and high-gain npn and pnp bipolar transistors. All of these components are implemented in a standard digital process without mask adders like deep nwell (DNWELL), silicide block (SIBLK), or dedicated high voltage (HV) transistor implants that are commonly used in the industry for deep sub-micron SOC implementation.

Impact of transistor reliability on RF oscillator phase noise degradation

The impact of deep sub-micron CMOS transistor reliability on RF oscillator phase noise degradation is demonstrated along with the importance of off-state drain stress for large signal RF applications. Process and device optimization was successful in reducing phase noise degradation to acceptable levels.