Greg C. Baldwin

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques

System on Chip (SoC) integration is the theme of the first integrated 3.5G baseband and multimedia applications processor fabricated using a low-power digital and analog design platform and 45nm process technology. This SoC supports mobile standards: HSUPA/HSDPA, WCDMA, EDGE/GPRS/GSM and applications such as MPEG-4 video streaming, Java and MP3 audio. The high- performance multimedia, multiprocessor engine includes an 840MHz ARM1176, a 480MHz TMS320C55x DSP, and a 240MHz image processor.

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (VT) variation, already a significant issue in todays advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local VT variation and achieve a reliable design with minimal pessimism.

Layout Variation Effects in Advanced MOSFETs: STI-Induced Embedded SiGe Strain Relaxation and Dual-Stress-Liner Boundary Proximity Effect

This paper reports two areas of focus for layout variation effects in advanced strained-Si technology: 1) shallow-trench isolation (STI)-induced embedded SiGe (eSiGe) strain relaxation and 2) impact of dual-stress-liner (DSL) boundary on channel mobility. A complete data analysis, including two different strain measurement techniques of nanobeam diffraction and geometric phase analysis, is presented, along with a quantitative understanding for each effect. It is reported that the eSiGe profile can have a significant impact on the STI proximity effect for p-MOSFETs and that DSL boundary proximity can cause significant channel mobility degradation for both n- and p-MOSFETs. Both effects result in the reduction in channel strain along the [110] direction.

Pocket Implant-Dependent Channel Mobility in Advanced p-MOSFETs With Strain Engineering

A new approach to channel mobility engineering using strained-Si technology is described with a complete data analysis. It is discussed that [110]/(100) Si channel mobility in p-MOSFET with embedded SiGe source/drain and compressive stress liner can be strongly dependent on pocket implant dose, resulting from a change in piezoresistance coefficient as a function of p-type carrier dopant concentration in the vicinity of the channel, whereas channel mobility of n-MOSFETs shows weaker dependence on pocket implant dose due to: 1) smaller piezoresistance coefficient of n-channel and 2) less channel strain relative to p-MOSFETs.