Thomas J. Snethen

Design of an efficient weighted random pattern generation system

This paper describes the design of an efficient weighted random pattern system. The performance of the system is measured by the number of weight sets and the number of weighted random patterns required for high fault coverage. Various heuristics that affect the performance of the system are discussed and an experimental evaluation is provided.

Simulator-oriented fault test generator

The problem of generating tests for sequential logic networks has become severe with large-scale integration (LSI). Since the internal gates cannot be tested by direct measurements, it is imperative that a rigorous logic test be developed to ensure quality at the chip level. The sequential complexity of many LSI chips exceeds the practical limitations of the familiar technique of modeling sequential logic for the application of combinational logic test-generation algorithms. Although other approaches, such as pseudo-random pattern generation, have been tried with some success, the pattern count may be quite large. This paper describes a method of test pattern generation that was developed with three objectives: to generate long pattern sequences systematically when needed, to model the sequential logic accurately so that any test generated would be valid, and to focus on assumed faults such as stuck 1 and stuck 0. Also discussed are the strengths and limitations of this method and some comparative results.

Advanced microprocessor test strategy and methodology

This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBMs high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached.

Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip

This paper describes the test tool methodology used for the IBM S/390 microprocessor. An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were required. This paper explains the techniques used to accomplish this along with explaining why the method was chosen and how it helped expedite the process.

A weighted random pattern test generation system

This paper describes a weight generation algorithm that is driven by tests created by a test generator. New concepts with regard to throwing away ineffective weight sets are developed as an integral part of the system. Various parameters that help improve the effectiveness of the weight generation system are discussed.

Minimizing the problem of logic testing by the interaction of a design group with user-oriented facilities

Early design decisions concerning logic packages often make subsequent testing difficult. To minimize such problems, logic designers must maintain close communication with those responsible for testing the finished product. This paper explores a user-oriented system which enables the designer to recognize and correct testing problems in the early stages of design.

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test

This paper describes how we provide a mean for dealing with the programmable aspects of on-product clock generation (OPCG) for use during ATPG and how that can also help with low power delay test. The system described in this paper automatically generates mode initialization sequence, setup sequence, test sequence and others and enables low power aware delay test when faster on product clocks are present on board. This system has successfully been used to process delay test for ASIC chips even with 22 PLLs on board.