Robert Dean Adams

A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-in self-test

An experimental 576 K BiCMOS emitter-coupled-logic (ECL)-compatible SRAM that achieves 3.5-ns access and cycle is discussed. The SRAM is fully self-testable using less than 1 K on-chip logic gates to assist characterization, wafer testing, and package testing. The I/O is also transistor-transistor-logic (TTL) programmable with the first-metal mask. >

Deterministic self-test of a high-speed embedded memory and logic processor subsystem

A memory built-in self-test state machine (MBIST) was designed to test multiple RAMs, each with differing characteristics with deterministic patterns. These memories are all tested in parallel with a BIST that uses a high-performance pipelined architecture to supply patterns from a single centralized memory BIST state machine at memory cycle speeds. After verifying the RAM integrity, the state machine generates the minimum set of deterministic patterns required to test the associated comparator logic and applies the patterns through the corresponding RAMs to accomplish a 100% stuck fault logic test.

Self test architecture for testing complex memory structures

The structural complexity and test challenges of complex dependent memory structures are described. An isolation strategy to minimize the test logic overhead and delay penalty is presented. A set of custom memory test algorithms is designed to test the memory cell, bridging and multi-port faults in complex dependent memory structures. A novel programmable memory BIST architecture to realize the developed custom memory test algorithms has been described. The proposed memory BIST architecture can be used to test the dependent memory structures in different stages of their fabrication and assembly. The experimental results demonstrate the area overhead of different components of the proposed programmable memory BIST architecture.

Bitline contacts in high density SRAMs: design for testability and stressability

Process scaling and the need for smaller SRAM cells challenges process technologies to make millions of robust and reliable bitline contacts on a single chip. Another challenge is to identify marginal, resistive and unreliable bitline contacts given the inherent electrical characteristics of the SRAM cell. This paper describes two design techniques that improve the screenability and stressability of bitline contacts in high-density SRAMs. These techniques are developed to overcome the lack of detectability of resistive bitline contacts in SRAM cells.

A 370-MHz memory built-in self-test state machine

Hardware and simulation results for a 370 MHz memory built-in self-test state machine are presented. Dynamic differential cascode voltage switch logic, unique clocking techniques, and logic pipelining were used to achieve the 370 MHz performance. Testing of multiple SRAMs and content addressable memories is accomplished with deterministic patterns generated by the state machine. Inclusion of a programmable pattern implemented via scan initialization provides test-pattern flexibility. Failing addresses are stored for redundancy implementation.<<ETX>>