Indranil Sen Gupta

Design of CAECC - cellular automata based error correcting code

A new scheme for designing error detecting and error correcting codes around cellular automata (CA) is reported. A simple and efficient scheme for generating SEC-DED codes is presented which can also be extended for generating codes with higher distances. A CA-based hardware scheme for very fast decoding (and correcting) of the codewords is also reported. >

CA-based byte error-correcting code

This paper reports a novel approach for designing byte error-correcting codes using cellular automata (CA). A simple scheme for generation and decoding of single-byte error-correcting and double-byte error-detecting codes, referred to as CA-SbEC-DbED, is presented. Extension of the scheme to locate/correct larger number of information byte errors has been also included. The encoding and decoding algorithms have been designed with the help of a linear operator that can be conveniently realized with a maximum length group CA. The regular, modular and cascadable structure of CA can be economically built with VLSI technology. Compared to the existing architecture of the Reed-Solomon decoder chip, CA-based implementation of the proposed decoding scheme provides a simple cost effective solution. >

Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks

All elliptic curve cryptographic schemes are based on scalar multiplication of points, and hence its faster computation signifies faster operation. This paper proposes two different parallelization techniques to speedup the GF(p) elliptic curve multiplication in affine coordinates and the corresponding architectures. The proposed implementations are capable of resisting different side channel attacks based on time and power analysis. The 160, 192, 224 and 256 bits implementations of both the architectures have been synthesized and simulated for both FPGA and 0.13@m CMOS ASIC. The final designs have been prototyped on a Xilinx Virtex-4 xc4vlx200-12ff1513 FPGA board and performance analyzes carried out. The experimental result and performance comparison show better throughput of the proposed implementations as compared to existing reported architectures.

Effect of glitches against masked AES S-box implementation and countermeasure

Masking of gates is one of the most popular techniques to prevent differential power analysis (DPA) of AES algorithm. It has been shown that the logic circuits used in the implementation of cryptographic algorithms leak side-channel information inspite of masking, which can be exploited, in differential power attacks. The phenomenon in CMOS circuits responsible for the leakage of masked circuits is known as glitching. Motivated by this fact, the authors analyse the effect of glitches in CMOS circuits against masked implementation of the AES S-box. The authors explicitly demonstrate that glitches do not affect always. There exists a relation between combinational path delay of the circuit and timing difference of input vectors to the circuit, which has a bearance on the amount of information leaked by the masked gates. A balanced masked S-box circuit is proposed where the inputs are synchronised by sequential components. Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked AES S-box against DPA attacks.

A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography

This paper presents the architecture and FPGA implementation of a robust GF(p) parallel arithmetic unit. The most efficient modular multiplication, inversion and division units greatly reduce the clock cycles requirement for point operations applicable to elliptic curve cryptography. The parallel arithmetic unit helps to achieve a high speed up in cryptographic applications. The architecture can resist the cryptographic timing attack. Integrated input and output interface units provide lower bandwidth requirement to plug in the architecture with automated cryptographic systems. The design exhibits its elegance among competitive architecture with respect to throughput and robustness.

Partial encryption and watermarking scheme for audio files with controlled degradation of quality

With the rapid progress in communication and multimedia technology, protection of multimedia assets has become a major concern. Encryption and watermarking are two complementary techniques that are used for safeguarding multimedia data like audio, video and images. These methods serve two different purposes; encryption helps in making the media unintelligible, while watermarking helps in providing copyright information in it. In this paper a combination of both encryption and watermarking is incorporated on audio files with this aim in view. Discrete Wavelet Transformation (DWT) is performed on audio files up to third level which gives rise to a binary tree like structure. The areas for watermark embedding and encryption are selected among the wavelet coefficients in the leaf nodes of the tree. Detailed experimentation is carried out with analysis of SNR values, that leads to the determination of degree of degradation of the audio quality after encryption. Such controlled degradation can be used for safe distribution of audio contents over public networks, whereby only the authorized users can have access to the high quality contents, while other users can only access a lower quality version.

Energy and performance evaluation of a dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip architecture

This paper proposes a new dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip design. It simplifies the router design as well. It results in significant saving in the energy consumed by the network. For uniform traffic, the saving is as high as 63%. It offers the flexibility of designing routers of different sizes for mapping of applications.

Genetic Algorithm based Scan Chain Optimization and Test Power Reduction using Physical Information

In this paper, we consider genetic algorithm to optimize the scan chain length of a given circuit and minimize the power dissipation during testing. For scan chain optimization, we use layout information so as to have a more accurate modeling of scan chain lengths. At the same time, we also try to minimize the test power by reducing switching activity in the scan flip-flops during scan test operation. The scan chain is partitioned into a specified number of sub chains in order to further minimize the scan chain length, routing overhead and test power. Experimental results have been reported on ISCAS-89 benchmark circuits

FPGA implementation of extended reconfigurable Binary Edwards Curve based processor

Elliptic Curve Cryptosystem (ECC) is the next generation public key ciphers for securing communications. However, due to its inherent complex mathematical nature, it poses challenges to designers. In this paper, we present a Field Programmable Gate Array (FPGA) design of scalar multiplication on Binary Edwards Curve (BEC) for state of the art field of GF(2233). The work contributes to develop shared data and control paths for the processor, to support two important curve operations, namely point halving and doubling based scalar multiplication. Such a unified design has the advantage of reduction in hardware and yet supporting both these important operations. To the best of our knowledge, this is the first reported design of a BEC based processor which supports both point halving and doubling. Detailed experimental results are provided to show that with minimal overhead the design can perform both point doubling and halving based scalar multiplications.

Modelling and simulation of combinational digital circuits using Petri nets

The P-model approach of modeling a combinational digital network using Petri nets is introduced. In this model a given logic circuit its represented by a graph With only two types of nodes, places and transitions. A logic 1 value in any line of the circuit corresponds to the presence of a so-called token, and a logic 0 corresponds to the absence of tokens, in the corresponding place of the P-model. The operation of the circuit is reflected in the execution of the P-model resulting from the firing of transitions. Several minimizing transformations in the P-model domain are discussed, which reduces the number of places and transitions by an order of magnitude. Based on this P-model representation of a logic circuit, a logic simulation algorithm is outlined. The method is faster and also simpler to implement than conventional simulation techniques.