Kantilal Bacrania

A 10b 50MS/s pipelined ADC with opamp current reuse

Power-saving techniques such as opamp current reuse and capacitive level shift reduce the power consumption of a 10b pipelined ADC to 220muW/MHz. A 50MS/S prototype in 0.18mum CMOS consumes 18mW (11mW for analog) at 1.8V and occupies 1.1times1.3mm2. The measured ENOB of the ADC is 9.2b (8.8b) for a 1MHz (20MHz) input

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 muW/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for 1- and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0deg to 85 degC and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1.1 times 1.3 mm2 using a 0.18-mum complementary metal oxide semiconductor (CMOS) process.

A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection

In the digital wireless SoC applications, CT DeltaSigma ADCs have been widely used for I/Q quantization due to the built-in anti-aliasing function and insensitivity to the input sampling error. They also offer higher-frequency performance than SC modulators as no critical opamp settling is required. CT modulators with low OSR have achieved a DR greater than 75 dB in a 20 MHz band. However, they all suffer from inaccurate active filtering as filter time constants are set by RC and C/Gm values that vary by as much as plusmn20 to 30%. By lowering OSR, the signal band can be widened, but the in-band zero of the NTF should be optimally placed to maximize the DR. Inaccurate NTF zero either degrades the DR or makes the modulator unstable. This work presents an exact time-constant auto-tuning method using an LMS algorithm. With a binary pulse dither injected into the loop at the input of the quantizer, the filter time constant can be calibrated continuously with crystal accuracy until the correlated residual pulse dither disappears in the digital output.

A 10-b 40-Msample/s BiCMOS A/D converter

A fully-differential, 10-b, 40-Msample/s pipelined analog-to-digital converter (ADC) has been developed and tested. The converter exhibits a signal-to-(noise+distortion) ratio (SNDR) of 57.1 dB and consumes 250 MHz is made possible with the open-loop sampling scheme.

Digital error correction to increase speed of successive approximation

A digital correction procedure that reduces the conversion time of a standard 12b A/D converter from 12μs to 7μs with but a 15% increase in die area will be presented.

Statistical correction of A/D converter errors

A method to correct the pipelined and multi-step A/D converter errors is proposed and implemented on a low-power 12-bit 10 M sample/s analog-to-digital converter. The converter consumes 315 mW from a single 5 V supply and exhibits wide input bandwidth, good linearity (DNL=-0.36 LSB), and low distortion with a spurious-free dynamic range (SFDR) of 83 dB.

A 14-b, 125 MSPS digital-to-analog converter and bandgap voltage reference in 0.5 /spl mu/m CMOS

A 14-bit, 125 MSPS (mega samples per second) digital-to-analog converter (DAC) implemented in a 0.5 /spl mu/m, 5 V single-poly triple-metal process is described. The DAC operates from a single 3 V to 5 V supply and can deliver up to 20 mA full-scale into a 50 /spl Omega/ load. Power dissipation with a 5 V Supply and 20 mA full-scale is 180 mW at a 125 MSPS clock rate, dropping to 90 mW with a 3 V supply. An on-chip bandgap voltage reference achieves a temperature coefficient of 30 ppm//spl deg/C and an output voltage standard deviation of 1%.

A CMOS 10 b 60 Msample/s ADC with ultra fast gain control

A 10-bit 60 Msample/s CMOS analog-to-digital converter (ADC) aimed at high-order system integration applications has been designed and fabricated. It features a single 5 V design, an internal sample-and-hold with gain programmable from 0 to 24 dB in 6 dB steps and has a full-power bandwidth (FPBW) of >250 MHz. The stand-alone version of the converter dissipates 400 mW of power.