Bang-Sup Song

A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator

A 1.1-GHz fractional-N frequency synthesizer is implemented in 0.5-/spl mu/m CMOS employing a 3-b third-order /spl Delta//spl Sigma/ modulator. The in-band phase noise of -92 dBc/Hz at 10-kHz offset with a spur of less than -95 dBc is measured at 900.03 MHz with a phase detector frequency of 7.994 MHz and a loop bandwidth of 40 kHz. Having less than 1-Hz frequency resolution and agile switching speed, the proposed system meets the requirements of most RF applications including multislot GSM, AMPS, IS-95, and PDC.

A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter

A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (*2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capacitor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of 1 Msample/s with 12 bits of linearity has been made and evaluated. A prototype pipelined A/D converter implemented using a double-poly 1.75- mu m CMOS process consumes 400 mW with a 5-V single supply and occupies 14 mm/sup 2/, including all digital logic and output buffers. >

Digital-domain calibration of multistep analog-to-digital converters

A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >

Background digital calibration techniques for pipelined ADCs

A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADCs) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDACs) commonly used in multistep or pipelined ADCs. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other self-calibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of self-calibrating multistep or pipelined ADCs. The proposed method improves the performance of the inherently fast ADCs by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, of amp DC gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a split-reference injection technique. Ultimately, the missing signal within two-thirds of the Nyquist bandwidth is recovered with 16-b accuracy using a forty-fourth order polynomial interpolation, behaving essentially as an FIR filter,.

A self-trimming 14-b 100-MS/s CMOS DAC

A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and dynamic linearity is presented. The DAC is based on a central core of 15 thermometer decoded MSBs, 31 thermometer decoded upper LSBs (ULSBs) and 31 binary decoded lower LSBs (LLSBs). The static linearity corresponding to the 14-b specification is obtained by means of a true background self-trimming circuit which does not use additional current sources to replace the current source being measured during self-trimming. The dynamic linearity of the DAC is enhanced by a special track/attenuate output stage at the DAC output which tracks the DAC current outputs when they have settled but attenuates them for a half-clock cycle after the switching instant. The DAC occupies 3.44 mm/spl times/3.44 mm in a 0.35-/spl mu/m CMOS process, and is functional at up to 200 MS/s, with best dynamic performance obtained at 100 MS/s. At 100 MS/s, power consumption is 180 mW from a 3.3-V power supply, and 210 mW at 200 MS/s.

CMOS RF circuits for data communications applications

The author describes the recent development of two analog CMOS circuits operating at RF frequencies with applications to data communications. One is a four-quadrant analog multiplier which exhibits a 100-MHz bandwidth with a measured linearity error of 0.7% for X and Y inputs of 0.6 and 0.8 V, respectively. The other is a 90/spl deg/ phase shifter which maintains the grain and phase errors of less than 0.5 dB and 3/spl deg/, respectively, for a signal within 40-60-MHz frequency range.

A 15 b 5 MSample/s low-spurious CMOS ADC

This 15b CMOS ADC at 5MSample/s has four stages with 5, 5, 5, and 6b each. The number of bits resolved per stage is set higher to achieve the same resolution with less accurate components. Resolving more bits per stage greatly simplifies op amp design and reduces the initial capacitor matching requirement. Furthermore, residue amplifiers with low feedback factors are less sensitive to summing-node parasitics. The first two 5b stages are calibrated using the remaining part of the ADC. Two stages are selected for calibration. The gain ofthe 5b residue amplifier is set to 16 to make room for digital correction. After digital correction, the chip has an 18b output. Performance up to 16b level can be tested after removing 2 LSBs corrupted by digital processing. System partitioning and multi-stage calibration solve two fundamental problems of capacitor matching and finite opamp gain.

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 /spl mu/m CMOS technology exhibits a DNL of /spl plusmn/0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm/sup 2/. >

A 14 b 100 Msample/s CMOS DAC designed for spectral performance

At 60 MSample/s, DAC SFDR is 80 dB for 5.1 MHz input signals and is down only to 75 dB for 25.5 MHz input signals. Previous DACs specified for operation at this speed and resolution have exhibited similar SFDR only at lower clock and/or signal frequencies. The DAC is implemented in a 0.8 /spl mu/m CMOS process (minimum gate length is 0.65 /spl mu/m), consumes 750 mW at 100 MSample/s speed, and utilizes a special output stage circuit to obtain dynamic performance.

A 48–860 MHz CMOS Low-IF Direct-Conversion DTV Tuner

A CMOS low-IF direct-conversion digital TV (DTV) tuner needs no off-chip harmonic rejection and image filters to receive both terrestrial and cable TV channels in the 48 to 860 MHz frequency range. Complex in-phase and quadrature (I/Q) poly-phase mixing together with coarse active RF filtering suppresses the third-harmonic mixing by 72 dB, and a digital LMS image correlation algorithm reduces the image leakage by 61 dB. A global AGC scheme keeps the signal level in the down-conversion mixer constant, and warrants the RF front-end linearity with strong blockers. Anti-aliasing and digital channel filters are made digitally programmable so that DTV standards with 6-8 MHz channel bandwidths can be supported. The measured system noise figure is 4-7 dB over the whole TV band. When measured at 500 MHz, the sensitivity is -86 dBm with ATSC-T 8-VSB signal, and the MER is 31.5 dB with actual J.83/B 256-QAM signal from a commercial CATV source. The chip implemented in 0.18 mum CMOS occupies 5times5mm2, and consumes 750 mW at 1.8 V.