Kaoru Mikagi

A new cobalt salicide technology for 0.15-/spl mu/m CMOS devices

A new cobalt (Co) salicide technology for sub-quarter micron CMOS transistors has been developed using high-temperature sputtering and in situ vacuum annealing. Sheet resistance of 11 /spl Omega///spl square/ for both gate electrode and diffusion layer was obtained with 5-nm-thick Co film. No line width dependence of sheet resistance was observed down to 0.15-/spl mu/m-wide gate electrode and 0.33-/spl mu/m-wide diffusion layer. The high temperature sputtering process led to the growth of epitaxial CoSi/sub 2/ layers with high thermal stability. By using this technology 0.15 /spl mu/m CMOS devices which have shallow junctions were successfully fabricated.

A thermally stable Ti-W salicide for deep-submicron logic with embedded DRAM

A new titanium-tungsten (Ti-W) salicide process with high-thermal stability has been developed for deep-submicron logic with embedded DRAM. The sheet resistance of 14 /spl Omega///spl square/ for Ti-5at%W silicide on both 0.18 /spl mu/m gate and 0.35 /spl mu/m diffusion layers was achieved. This is the lowest resistivity (50 /spl mu//spl Omega/-cm) in C49-TiSi/sub 2/, and did not change during annealing at 800/spl deg/C for 1 hour. By adding W atoms in Ti, high-thermal stability of the metastable C49-TiSi/sub 2/ was obtained, so that the C49-TiSi/sub 2/ did not transform to the C54-TiSi/sub 2/ phase below 900/spl deg/C. 0.18 /spl mu/m CMOS transistors were successfully fabricated using the Ti-W salicide technology.

A new cobalt salicide technology for 0.15 /spl mu/m CMOS using high-temperature sputtering and in-situ vacuum annealing

A new cobalt (Co) salicide technology using high-temperature sputtering and in-situ vacuum annealing process has been developed. This technology is a simple process without additional ion implantation and metal deposition to promote silicidation and to suppress oxidation of Co film. No line width dependence of sheet resistances was achieved down to for 0.15 /spl mu/m gate electrode and 0.33 /spl mu/m for diffusion layer. Sheet resistance of 11 /spl Omega//sq. for both gate electrode and diffusion layer was obtained with 5 nm thick Co film (CoSi/sub 2/ 17.5 nm). By using this technology, 0.15 /spl mu/m CMOS devices which have shallow junctions were successfully fabricated.

A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cell

This paper presents a 0.18-/spl mu/m merged DRAM/Logic technology having a 0.45-/spl mu/m/sup 2/ stacked capacitor cell. A low-temperature Metal/Insulator/Silicon (MIS) capacitor process provides high storage capacitance in the small cell, as well as a fully compatible process with high-performance CMOS logic technologies. A robust Co-salicide technology eliminates additional process steps for a silicide block. A developed 4 Mbit test vehicle achieves a retention time of 16 ms at 110/spl deg/C even with a CoSi/sub 2/ layer remaining on all diffusion regions in the memory cells.