Masamoto Tago

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13

Ultra-high-density interconnection technology of three-dimensional packaging

Abstract The study of 20-μm-pitch interconnection technology of three-dimensional (3D) packaging focused on reliability, ultrasonic flip–chip bonding and Cu bump bonding is described. The interconnection life under a temperature cycling test (TCT) was at an acceptable level for semiconductor packages. Failure analysis and finite element analysis revealed the effect of material properties. Basic studies on ultrasonic flip–chip bonding and very small Cu bump formation were investigated for low-stress bonding methods. The accuracy of ultrasonic flip–chip bonding was almost the same level as that of thermocompression bonding and the electrical connection was also confirmed. Atomic-level bonding was established at the interface of Au bumps. For Cu bump bonding, a dry process was applied for under bump metallurgy (UBM) removal. Electroless Sn diffusion in Cu was investigated and the results clarified that the intermetallic layer was formed just after plating. Finally, we succeeded in building a stacked chip sample with 20-μm-pitch interconnections.

Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20 µm Pitch

Superfine flip-chip bonding technologies in 20 µm pitch microbumps on copper through-hole electrodes are substantial technologies for three-dimensional (3D) chip stacking LSI. As the advanced interconnection technology to connect the through-hole electrodes at low temperature and low bonding force, the ultrasonic flip-chip bonding (UFB) was verified by the total evaluation and the atomic-level analysis of the bonding interface on the chip-on-chip (COC) structure utilizing electroplated Au microbumps in 20 µm pitch. First, the lower limit bonding conditions were confirmed to be a bonding force of 20 N and an amplitude of 3 µm; the bonding accuracy achieved was within ±2 µm, the electrical interface resistance was stable about 0.57 Ω, and no damage around the interconnection structure was observed. Secondly, the mechanism of solid phase bonding interface formation at the atomic level without solid phase diffusion was confirmed as the Au-Au solid phase UFB bonding mechanism, and the orientation geometry of such bonding was apparently different from that of thermo compression bonding, which showed solid phase diffusion across the boundary. The achievement of this research will enable the realization of the 3D chip stacking LSI in the near future, which is characterized by scalabilities and high-performance. The subjects are the elucidation of the real oscillation contributes to bonding to optimize the process conditions and the establishment of the micro joint reliabilities utilizing UFB process.

Ultra-high-density 3D chip stacking technology

The 3D chip stacked LSI technology under development in ASET is a new packaging technology to realize highdensity and high-speed transmission. Two key technologies is necessary to realize the 3D chip stacked LSI. One is low temperature simple interconnection of Cn through electrodes in 20 pm pitch. Other is encapsulation of super narrow gap less than 10 pm between devices. The Cu bump bonding (CBB) process utilizing Sn capped Cu Bump was evaluated, and connection at 245°C and 150T by formation of the inter metallic compound (IMC) as qCu&n5 was confumed. The post aging process was applied to form the complete diffusion layer between Cn bumps after bonding, and the IMC layer was only consist of E-Cu,Sn, and considered to be stable against the thermal stress after chip stacking process. In addition, the non-conductive particle paste (NCP) preform process was evaluated. The micro thin gap was almost encapsulated without void. ,Moreover the chip backside warpage after bonding was very small less than 3 pm, and considered to realize stacking chip onto the stable bonding area. Finally, The mechanical sample of 3D chip stacked module with Cu through electrodes in 20 pm pitch was build snccessfidly utilizing CBB and NCP preform process.

A novel "SMAFTI" package for inter-chip wide-band data transfer

A package structure with inter-chip connection is proposed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a fine-wiring pattern and ultra-fine-pitch through vias. The FTI is formed on a silicon wafer using a photolithography process to realize fine vias and fine wiring patterns. This structure enables over a thousand inter-chip connections and a high pin count in the logic device. This paper describes the concept, structure, process, and experimental results of prototypes of this package called SMAFTI (SMArt chip connection with FeedThrough Interposer). This paper also reports the results of intermetallic compound analysis and thermal cycle test (TCT) that were performed to confirm the fundamental reliability of this novel inter-chip connection structure

Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation

The advanced 3D stacking technologies are discussed in this paper. They are the microbumping in 20 /spl mu/m pitch, the basic processes of the advanced bonding processes for the high precision and the reliable interconnections, the novel technologies to encapsulate the layered microthin gaps less than 10 /spl mu/m, and the non-destructive inspection. These technologies are confirmed to realize the 3D stacked LSI structure, and it will be expanded to the advanced system packaging technologies in the near future.

Daisy Chain for Power Reduction in Inductive-Coupling CMOS Link

This paper discusses a daisy chain of current-drive transmitters in inductive-coupling CMOS links. Current is reused by multiple transmitters. 8 transceivers are arranged with a pitch of 20mum in 0.18mum CMOS. Transmit power is saved by 35% without sacrificing data rate (1Gb/s/ch) and BER (<10-12) by having 4 transmitters daisy chained

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing

The cost for screening test on wafer has continually increased each year; the test cost especially for low-price IC chips, for example, exceeds one-third of total chip cost. Furthermore, screening test on wafer to select good dies (Known-Good-Die) will become more significant to improve the yields of up-to-date packages such as Chip-on-Chip and 3D-LSI. Therefore, the cost reduction for screening test will be a key issue to maintain continuous LSI-performance scaling.

Copper bump bonding with electroless metal cap on 3 dimensional stacked structure

CBB, the copper bump bonding process, can perform flip-chip bonding in 100 /spl mu/m pitch with a thin electroless metal cap on the surface, leading to interconnection of the copper through-hole electrodes on a 3D stacked structure. In this paper, the results of the technical studies on both the electroless plating process and the thermo-compressive bonding process are introduced, which are key technologies for expansion to interconnections with 20 /spl mu/m pitch to realize advanced 3D stacked structures.