Raghuram V. Pucha

Design and demonstration of low cost, panel-based polycrystalline silicon interposer with through-package-vias (TPVs)

This paper for the first time proposes and demonstrates the use of panel-based polycrystalline silicon interposers for highest I/Os at lowest cost. Such an interposer is targeted at roughly a 10× lower cost compared to wafer based silicon interposers with through silicon vias (TSVs) and back end of line (BEOL) re-distribution layers (RDL). Laser via ablation was used to demonstrate through package vias (TPVs) as small as 10μm diameter in 220μm thin polycrystalline silicon panels made without any chemical-mechanical polishing (CMP). A thick polymer via liner and stress buffer layer was formed in the silicon TPVs to replace oxide liners and diffusion barriers used in TSVs. A panel silicon interposer test vehicle process demonstrator was fabricated and initial electrical measurements indicate much lower loss compared to CMOS silicon interposer with thin oxide liners. Electrical and mechanical design and modeling was also carried out to provide design guidelines for TPV formation.

Effect of Interphase Modulus and Nanofiller Agglomeration on the Tensile Modulus of Graphite Nanoplatelets and Carbon Nanotube Reinforced Polypropylene Nanocomposites

This study investigates the effect of filler content (wt%), presence of interphase and agglomerates on the effective Young’s modulus of polypropylene (PP) based nanocomposites reinforced with exfoliated graphite nanoplatelets (xGnP ) and carbon nanotubes (CNTs). The Young’s modulus of the composites is determined using tensile testing based on ASTM D638. The reinforcement/polymer interphase is characterized in terms of width and mechanical properties using atomic force microscopy which is also used to investigate the presence and size of agglomerates. It is found that the interphase has an average width of ~ 30 nm and modulus in the range of 5 to 12 GPa. The Halpin-Tsai micromechanical model is modified to account for the effect of interphase and filler agglomerates and the model predictions for the effective modulus of the composites are compared to the experimental data. The presented results highlight the need of considering various experimentally observed filler characteristics such as agglomerate size and aspect ratio and presence and properties of interphase in the micromechanical models in order to develop better design tools to fabricate multifunctional polymer nanocomposites with engineered properties.

Thermomechanical reliability of underfilled BGA packages

The effect of underfill on various thermomechanical reliability issues in super ball grid array (SBGA) packages is studied in this paper. Nonlinear finite element models with underfill and no underfill are developed taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled temperature and direction-dependent, as appropriate. The stress/strain variations in the package due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The effect of copper core on the solder ball strains is presented. The possibility of delamination at the interposer-underfill interface as well as substrate-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA packages. The predicted number of thermal cycles to solder joint fatigue are compared with the existing experimental data on similar nonunderfilled BGA packages.

Damage Metric-Based Mapping Approaches for Developing Accelerated Thermal Cycling Guidelines for Electronic Packages

The accumulated equivalent inelastic strain per cycle and the maximum strain energy density over one cycle have been used as damage metrics to map the solder fatigue damage during Field-Cycling (FC) and Accelerated Thermal Cycling (ATC) simulations. The objective of this work is to develop accelerated thermal cycling guidelines for flip-chip on board and flip-chip chip-scale electronic packages used in, for example, automotive applications. The percentage contributions of plastic and creep strains to the total inelastic strain and contributions within the accelerated cycling are used as a basis for developing modified accelerated thermal cycles. Different temperature regimes are explored to match the contributions of plastic and creep strains to total inelastic strain during field-cycling and accelerated thermal cycling and to reduce the time required for accelerated thermal cycling. The process mechanics of component assembly, time-and temperature-dependent material behavior and critical geometric features of the assembly are taken into consideration while developing the comprehensive virtual accelerated thermal cycling methodology.

Accelerated thermal cycling: is it different for lead-free solder?

Accelerated test parameters such as extreme temperatures, temperature range, temperature ramps and dwell times have a major influence on deformation mechanisms in solder joints. With the increasing push for the introduction of lead-free solders, there is a need to revisit the accelerated thermal cycling regimes, as the solder composition can also influence the deformation mechanisms in solder joints. Time independent plastic deformation due to dislocations leading to slip bands and time dependent creep deformation due to diffusional flow of vacancies leading to grain boundary sliding are the two primary deformation mechanisms in solder joints. It is recognized, for example, that the lead-free solders creep 10 to 100 times slower than tin-lead solders under a given stress state. This paper examines the inelastic deformation mechanisms in lead and lead-free solders in BGA packages. Accelerated thermal cycling guidelines have been developed keeping in perspective the field-use conditions. The accelerated thermal cycles developed mimic the solder deformation mechanisms as in the field-use conditions and also reduce the time and the cost associated with accelerated testing. The finite-element models developed in this work are validated using experimental thermal cycling data and Moire interferometry data.

Next generation of package/board materials technology for ultra-high density wiring and fine-pitch reliable interconnection assembly

Current board technologies are inherently performance-limited (FR-4) or cost-prohibitive (Al/sub 2/O/sub 3//AlN). New package or board materials with low CTE and high elastic modulus are needed for the next generation of high-performance convergent Microsystems to be able to fabricate ultra high-density wiring without big capture pads and to assemble area-array flip-chips with minimal stress on solder joint or perhaps completely eliminate underfills around the solder joint. A novel manufacturing process has been demonstrated to yield large-area thin carbon-silicon carbide (C-SiC) based composite boards with potentially low cost and desired thermomechanical properties - ultra high modulus, Si-matched CTE and large-area manufacturability. The reliability performance of this material was evaluated with flip chip test vehicle using conventional epoxies and advanced dielectrics such as BCB and PPE. Bumped dies were assembled and liquid-liquid thermal shock tests and Shadow Moire measurements were carried out to assess the solder joint reliability of these boards. In parallel with experiments, numerical models were also developed to analyze warpage, dielectric cracking and solder fatigue failure, and provide design guidelines. Though boards with Si-matched CTE are essential to lower the solder joint strains, they result in a high CTE mismatch between the build-up dielectrics and board, generating higher stresses in the dielectric which could lead to cracking. In this work, we show that dielectric cracking can be minimized with stiffer boards and thinner build-up layers. Based on the results, it can be inferred that high board stiffness and low CTE (/spl sim/3-4 ppm//spl deg/C) are needed to ensure reliability of high-density packages without the use of underfill. The test vehicle evaluation supported by modeling results indicate that the novel low-cost large-area processable ceramic matrix composite (C-SiC) has potential to be a promising candidate substrate material for next-generation microsystems.

Field-use conditions vs. thermal cycles - a physics-based mapping study

A physics-based approach that maps the solder damage induced through accumulated inelastic strain or accumulated strain energy density under field-use conditions with thermal cycling conditions has been developed. Various representative packages - Super Ball Grid Array (SBGA), Flip Chip Chip Scale Package (FCCSP), and Flip Chip On Board (FCOB) have been analyzed using the mapping methodology for automotive, military avionics and implantable medical device applications. In-house experimental data has been used to validate the modeling methodology and the approach presented. As the plastic and the creep deformation are fundamentally different, alternative accelerated thermal cycling profiles have been developed to mimic the solder damage and degradation during field-use thermal conditions.

Study on the Choice of Constitutive and Fatigue Models in Solder Joint Life Prediction

Various constitutive and fatigue-life predictive models for lead-tin solders in SBGA (Super Ball Grid Array) packages are studied and compared with the results from experimental data. Two solder compositions, 62Sn/36Pb/2Ag and 63Sn/37Pb are studied in this work. The fatigue life of 62Sn/36Pb/2Ag solder is studied using different constitutive models that take into consideration both the time-independent and time-dependent behavior of the solder. The fatigue life of 62Sn/36Pb/2Ag solder is predicted using an energy-based predictive model and compared with the experimental data. The choice of various predictive models on the solder joint life is studied using 63Sn/37Pb solder. Various predictive models, available in the literature, for eutectic and near eutectic solder compositions are studied to predict the fatigue life. Guidelines are provided for selecting constitutive and predictive models with appropriate damage metrics.© 2002 ASME

System-on-a-package (SOP) substrate and module with digital, RF and optical integration

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, and optical system integration on a single package. SOP aims to utilize the best of on-chip SOC integration and package integration to achieve the highest system performance at the lowest cost. The micro-miniaturized multi-functional SOP package is highly integrated and fabricated on large area substrates similar to the wafer-to-IC concept. In addition to novel mixed signal design methodologies, SOP research at PRC is targeted at developing enabling technologies for package level integration including ultra-high density wiring, embedded passive components, embedded optical interconnects, wafer level packaging and fine pitch assembly. Several of these enabling technologies have been recently integrated into the first successful system level demonstration of SOP technology using the intelligent network communicator (INC) testbed. This paper reports on the latest INC and SOP testbed results at the PRC and provides an insight into the future SOP integration strategy for convergent microsystems. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation.

System-level reliability assessment of mixed-signal convergent microsystems

The next-generation convergent microsystems, based on system-on-package (SOP) technology, require up-front system-level design-for-reliability approaches and appropriate reliability assessment methodologies to guarantee the reliability of digital, optical, and radio frequency (RF) functions, as well as their interfaces. Systems approach to reliability requires the development of: i) physics-based reliability models for various failure mechanisms associated with digital, optical, and RF Functions, and their interfaces in the system; ii) design optimization models for the selection of suitable materials and processing conditions for reliability, as well as functionality; and iii) system-level reliability models understanding the component and functional interaction. This paper presents the reliability assessment of digital, optical, and RF functions in SOP-based microsystems. Upfront physics-based design-for-reliability models for various functional failure mechanisms are presented to evaluate various design options and material selection even before the prototypes are made. Advanced modeling methodologies and algorithms to accommodate material length scale effects due to enhanced system integration and miniaturization are presented. System-level mixed-signal reliability is discussed thorough system-level reliability metrics relating component-level failure mechanisms to system-level signal integrity, as well as statistical aspects.