Karan Singh Bhatia

Tutorial 1A: Design challenges for the Internet of Things

The term “the Internet of Things” was first used in 1999 to refer to a network of objects embedded with sensors and wireless connectivity. By 2015, there were 5 billion of these connected devices. Within the next five years, it is predicted that there will be more than 25 billion connected IoT devices. This rapid market growth has been made possible by many innovations in connectivity standards, system architecture, power management, and circuit design. This talk will describe seven different design challenges and the solutions that have been needed for the creation of todays low power, small size, and low cost wireless sensors nodes. These challenges include reducing sleep current, improving power management efficiency, improving the sleep timer frequency stability, reducing startup time, connectivity standard optimization, reducing active power, and removing external components. The impact of each improvement to the over all system performance will be described, as well as examples of state-of-the-art designs in each of these areas. Further advances that are needed to continue this market growth will also be presented.

Tutorial 4B: ADC design - from system architecture to transistor level design

Pipelined and Delta-Sigma (ΔΣ) ADCs are increasingly becoming popular in mixed-signal system-on-chip (SoCs). This tutorial combines theoretical as well as practical perspectives on ADC design with special focus on two types of ADCs, viz., CT-ΔΣ ADC and pipelined ADC. The goal is to provide a complete picture to the audience, starting from system level architecture to their transistor-level design. The tutorial will cover basics of ΔΣ modulation, both continuous-time (CT) as well as discrete-time, and pipelined ADCs. System-level behavioral modeling using Matlab/Simulink environment will be presented. The top-down design approach will discuss circuit implementation and include circuit non-idealities in the behavioral modeling. Case studies will be presented for CT ΔΣ ADCs and various digital calibration techniques for pipelined ADCs.

Welcome message from the technical program chairs

It is our pleasure to warmly welcome you to the 29th IEEE International System-on-Chip Conference. The 2016 edition of the SoC conference is hosted in the beautiful city of Seattle, WA (USA). The Seattle area is a hot-bed of technology research and development with companies such as Amazon, Boeing, and Microsoft as well as universities like the University of Washington calling it home. With such a large concentration of talented engineers and with the conference theme being “Systems-on-Chip to Build the Internet of Things from the Ground Up”, it really is the ideal place to hold the SoC Conference.

Tutorial: The uncertain end to silicon

Summary form only given. As silicon technology moves progressively to ever smaller geometries, the uncertainties in the devices, due to atomic level imperfections and processing options become an ever larger factor in the design of systems-on-chip. The variabilities, mismatch and noise of 20nm and below process geometries dominate the design of these integrated circuits, affecting memory circuitry, analog blocks, digital logic and RF interfaces. We here discuss design practices to minimize systematic and random mismatch in memory blocks. We also discuss the emergence of Random Telegraph Noise in memory units. Design techniques for analog modules susceptible to mismatch and noise are considered, as are logic operation, guardbanding and operating stresses in the presence of these design uncertainties. RF operation is highly susceptible to phase noise issues, and limits, and mitigation methods are described. All these effects mean longer design cycles, and require operating safety margins that reduce the effectiveness of moving to the next process node. We investigate the question of whether it will be this type of process effect that will eventually stop silicon technology from advancing further.

FEC-based 4 Gb/s backplane transceiver in 90nm CMOS

This paper presents the first reported design of a forward error correction (FEC)-based high-speed serial link. A 4 Gb/s line rate transceiver in 90nm CMOS is designed with short block length BCH codes. FEC is shown to be effective for high code rates, high information rates and low SNR channels. Measurement results of the transceiver over a 18.2 dB Nyquist loss channel show a 45× reduction in minimum BER, and an increase in jitter tolerance at low transmit swings. For a BER <; 1012, the addition of FEC reduces the required transmit signal swing, from approximately 0.75 Vppd to less than 0.5 Vppd.