Neeraj Nayak

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented.

Highly-linear FM transmitter for mobile application in 65nm CMOS

An FM frequency synthesizer and antenna driver with >63dB SNR, <0.1% THD, and −dBc out-of-band emissions at 124dBµV output swing in 65nm digital CMOS is described. The optimized FLL incorporates a DCO with a highly linear capacitor array and flicker noise reduction techniques. Cascaded filtering and a segmented driver improve efficiency and tuning range with minimal high-order distortion.

Design of Low Power Digital Phase Lock Loops

Until recently, a vast majority of PLLs have been Analog PLLs (APLLs). The block schematic of a commonly used APLL is shown in Fig. 1. Here, divided versions of an input reference clock and the output of a Voltage Controlled Oscillator (VCO) are compared in Phase Frequency Detector (PFD), which in conjunction with a Charge Pump and a low pass loop filter generates a control signal for the VCO. This results in a phase lock between REFINT and FBCLK, making fo,t equal to M/NQ times fREF. Thus, the output frequency can be programmed by means of M, N and Q.