Karey L. Holland

Submicron wiring technology with tungsten and planarization

A submicron wiring technology has been designed, built, and proven reliable. This fully integrated technology features CVD-tungsten (W) and planarization. Vertical W studs maximize density by reducing contact/via ground rules and by facilitating the use of thick insulators for minimum capacitance. Complementary insulator and W planarization eliminate steps and ease patterning. As a result, circuit performance is enhanced without sacrificing yield or reliability.A versatile wiring technology has been developed which is suitable for high-density memory and multilevel logic applications. This fully integrated technology features CVD-tungsten (W) and planarization. Virtual W studs maximise density by reducing contact/via ground rules and by facilitating the use of thick insulators for minimum capacitance. Complementary insulator and W planarization eliminate steps and ease patterning. As a result, circuit performance is enhanced without sacrificing yield or reliability. The chosen materials and process combinations make possible aggressive metal pitch for DRAM, reliable space saving vertical studs for contact/via intensive SRAM, and provide vertical wiring for high-density multilevel logic. Device and reliability results are presented.<<ETX>>

Deep-ultraviolet lithography for 500-nm devices

Each DRAM design generation has required higher reoiution imaging and overlay capability. The 500-nm lithographic ground rules of a 16-Mb chip make deep-UV (DUV) an attractive alternative to,thc more stanth,rd mid-UV (MUV) photolithography presently practiced for less demanding technologies. The shorter wavelength permits an unproved depth of focus by allowing the same resolution at smaller numerical apertures. This approach retains the simplicity of single-layer-resist processing rather th a ii forcing conversion to m ultilayer imaging.

Isolated-grouped linewidth bias on SVGL Micrascan

Isolated to grouped linewidth bias is an important factor in determining the capability of an exposure tool. The process latitude can be significantly improved by minimizing the bias for small geometries (0.5 micron and less). The data presented here optimizes process related performances of SVGL Micrascan I (0.5 micron) and Micrascan II (0.35 micron). The work takes into account different contributions to the overall linewidth bias using modeling of aerial images and resist profiles. Experimental results are presented for positive and negative resists on Micrascan I, and positive resist on Micrascan II. The bias for aerial image is predicted by a model. The post-develop bias depends on the process conditions and the resist system used. Optimized processes are used on Micrascan I and II, and data on different substrates are presented.

Manufacturing implementation of deep-UV lithography for 500-nm devices

Lithographers have steadily reduced exposure wavelength and increased numerical aperture (NA) to maintain process window and simplicity. The G-line systems of the 1970s gave way to the I-line systems of the late 80s, and then to the deep ultraviolet (DUV) systems of today. This paper describes our characterization of a DUV lithography system for the manufacture of 16-Mb DRAM chips at 500-nm ground rules. The process consists of a positive-tone, aqueous-base developable photoresist with an overcoat for sensitivity control, and an anti- reflective coating (ARC) on selected levels. The exposure tools used are step-and-scan systems with a 0.36 NA and expose bandpass of 240 - 255 nm. Apply and develop processes are clustered with the expose tool to minimize defects, reduce cycle time, and eliminate process variables.