Karl L. Wang

Universal-V/sub dd/ 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

A universal-V/sub dd/ 32-kB four-way-set-associative embedded cache has been developed. A test cache chip was fabricated by using 0.18-/spl mu/m enhanced CMOS technology, and it was found to continuously operate from 0.65 to 2.0 V. Its operating frequency and power are from 120 MHz and 1.7 mW at 0.65 V to 1.04 GHz and 530 mW at 2.0 V. The cache is based on two new circuit techniques: a voltage-adapted timing-generation scheme with plural dummy cells for the wider voltage-range operation, and use of a lithographically symmetrical cell for lower voltage operation.

A 21-ns 32 K/spl times/8 CMOS static RAM with a selectively pumped p-well array

The design and performance of a 32 K/spl times/8-b CMOS static RAM (SRAM) are presented. The design features a selectively pumped p-well array. Using this array technology, high-impedance polysilicon resistor loads can be used to reduce the array standby current by three orders of magnitude, and the device characteristics can be optimized to achieve high speed in the peripheral circuits. A unique divided-word-line architecture with shared sense amplifiers is used to achieve high-speed read operation. The read speed is further enhanced by a novel quasistatic equalization that minimizes peak current. A high-speed write circuit with a write-to-read transition detection is used to achieve a fast write operation. An advanced 1.2-/spl mu/m double-level-metal CMOS technology was used to fabricate the devices. The access time is 21 ns and the active power is 330 mW at 22 MHz.

A 21ns 32K×8 CMOS SRAM with a selectively pumped P-well array

A selectivity pumped P-well array used in a 32K×8 CMOS SRAM with a divided-word line block architecture to achieve a 21ns access time, will be described. The chip (6.83×8.97mm) was processed in a 1.2μm double-level metal, twin-well CMOS technology. Active power is 330mW at 22MHz.