Katia R. A. Sasaki

Temperature influence on UTBOX 1T-DRAM using GIDL for writing operation

This paper investigates the temperature influence on Ultra Thin Buried Oxide (UTBOX) FDSOI devices used as a 1T-DRAM (single transistor dynamic random access memory cell) using GIDL (Gate Induced Drain Leakage) for writing operation through numerical simulations. At higher temperatures, it is observed that the memory window varies and the retention time is degraded, when using a standard read. To solve this issue, we suggest the ZTC read, which fixes the state-0 current independently of the temperature. Moreover, considering I0 current as a reference current for the memory cell operation results in improved retention time.

Ground plane influence on enhanced dynamic threshold UTBB SOI nMOSFETs

This paper investigates the ground plane influence on Ultra Thin Body and Buried Oxide (UTBB) FDSOI devices applied in a dynamic threshold voltage (DT) operation (V_B=V_G) over the conventional one (V_B=0V). The ground plane in enhanced DT (eDT), where the back gate bias is a multiple value of the front gate one (V_B=k×V_G) and the inverse eDT mode (V_G=k×V_B) were also considered and compared to the other configurations. The presence of the Ground Plane region in all DT configurations results in superior DC parameters like on-current/off-current ratio, a steeper subthreshold slope and a higher transconductance.

Influence of underlap on UTBB SOI MOSFETs in dynamic threshold mode

This paper discusses the influence of extensionless lengths (0nm-self aligned, 15nm and 20nm) on UTBB (Ultra-Thin-Body-and-Buried oxide) SOI (Silicon-On-Insulator) devices operating in conventional (VB=0V), Dynamic Threshold (DT2, where VB=VG) and enhanced Dynamic Threshold (eDT, where VB=kVG) modes. The extensionless device of 20nm (underlap between gate and source/drain) presents better SS (Subthreshold Swing), DIBL (Drain Induced Barrier Lowering), GIDL (Gate Induced Drain Leakage), transistor efficiency (gm/ID), VEA (Early Voltage) and AV (Intrinsic Voltage Gain). A large improvement was also observed experimentally when these devices operate under DT2 and eDT modes thanks to better coupling between the front and back gates, except for the GIDL that degrades due to a higher tunneling current near the drain caused by the higher transversal electric field.

Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices

This paper investigates the drain read bias impact on the FB-BRAM performance of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices. Both simulations and experimental results are used. Two read regimes are clearly observed. In the read regime at higher drain voltage, impact ionization is occurring and this result in a higher sense margin and a lower retention time compared to the low drain voltage read regime.

Enhanced dynamic threshold UTBB SOI at high temperature

This work focuses on the high temperature analysis in extensionless ultra-thin body and buried oxide (UTBB) SOI MOSFETs in dynamic threshold (DT) mode, as well as in enhanced DT (eDT) mode operation for the first time. In spite of the higher transconductance temperature degradation factor (c), the DT and eDT operations resulted in a lower VT variation with temperature and a lower Zero-Temperature-Coefficient (ZTC) point with the same current level for all k-values. Concerning the analog parameters, the transistor efficiency (gm/ID), Early voltage (VEA) and intrinsic voltage gain (Av) were degraded at high temperature. However, the improvement thanks to DT and eDT modes compensates and further enhances these parameters.

Back Enhanced (BE) SOI MOSFET under non-conventional bias conditions

The aim of this work is to investigate the working principle of the new Back Enhanced (BE) SOI MOSFET, under non-conventional bias conditions. This planar BE SOI device with undoped source/drain/channel structure presents the advantage to have very simple fabrication process (without any implantation and electron beam lithography) and can act like a p- or n-type MOS, depending on the back-gate bias condition. Under non-conventional bias condition, many electrical parameters present different behavior. The threshold voltage increases linearly with the drain to source voltage (VDS) if VDS > 0 and it is constant if VDS<0 in case of p-type BE SOI MOSFET and, analogously, the threshold voltage increases linearly with VDS if it is negative and it is constant if VDS>0 in case of a n-type BE SOI MOSFET. This fact is explained through experimental and simulated data.

Is there a kink effect in FDSOI MOSFETs

Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the potential was probed to evidence the role of majority carrier excess during the kink effect onset.

Body factor scaling in UTBB SOI with supercoupling effect

Focusing on the channel length scalability, this paper analyzes the coupling coefficient (body factor) in thick (25nm) and thin (7nm) UTBB SOI devices. Experimental data and simulations demonstrate that the supercoupling effect further improves the device scalability and operation in thin silicon films. The impact of thinning the gate oxide and body on the inter-channel coupling is also documented.

Influence of source-drain engineering and temperature on split-capacitance characteristics of FDSOI p-i-n gated diodes

Motivated by the TFET (tunneling field effect transistor) technology, we investigate the temperature and gate overlap/underlap influence on the capacitance of p-i-n diodes fabricated with UTBB FDSOI. The underlap-overlap architecture modifies the split capacitance curves essentially when the back interface is depleted. As a result, the extracted front gate oxide (tOX) and silicon film thickness (tSi) are accurate, with error below 5%. At high temperature, the capacitance curves are narrower due to the threshold voltage (VT) lowering in n- and p-channels. However, the accuracy of tOX and tSi extraction is only marginally affected.